Prosecution Insights
Last updated: April 19, 2026
Application No. 18/626,229

SEMICONDUCTOR DEVICE WITH ELONGATED PATTERN

Non-Final OA §102
Filed
Apr 03, 2024
Examiner
HO, TU TU V
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 12m
To Grant
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
1261 granted / 1347 resolved
+25.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
12 currently pending
Career history
1359
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
37.7%
-2.3% vs TC avg
§102
49.3%
+9.3% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1347 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 2. Claims 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. U.S. Patent Application Publication 2018/0158930 A1 (the ‘930 reference). Referring to claim 16, the ‘930 reference discloses a semiconductor device, comprising: a semiconductor fin (102, 104, Fig. 1, para [40] (paragraph(s) [0040])) extending from a substrate (106); a gate structure (not depicted in Fig. 1, depicted as gate 208 in Fig. 2A, and note that in Fig. 2, semiconductor fins are 202, para [47]) extending across a channel region (not depicted, and as known in the pertinent art) of the semiconductor fin (102); a plurality of isolation regions (108, para [40]) on opposite sides of the semiconductor fin (102, 104) and having top surfaces lower than a top surface of the channel region of the semiconductor fin (the channel region, not depicted, is a region between adjacent source/drain epitaxial structures 110A-C (as known in the pertinent art); thus, a top surface of each the isolation structures 108 is lower that a top surface of the channel region of the semiconductor fin); a source/drain epitaxial structure (110A, 110B, 110C, para [40]) over the semiconductor fin (102, 104); and a source/drain contact (contact metal 112, para [40]) over the source/drain epitaxial structure (110A, 110B, 110C), from a first cross-sectional view (of Fig. 1 (c)) taken along a first direction, the source/drain contact (112) wrapping around at least three sides of the source/drain epitaxial structure (110C) and in contact with the isolation regions (108). Referring to claim 18, the reference further discloses that, from a second cross-sectional view (of Fig. 1 (a) taken along a second direction perpendicular to the first direction, the source/drain contact (112) is entirely above the source/drain epitaxial structure (110A). Allowable Subject Matter 3. Claims 1-15 are allowable over the prior art of record. Claims 17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor device with all exclusive limitations as recited in claims 1, 11, 17 and 19, which may be characterized (claim 1) in that the first short sides are shorter than the first long sides and more curved than the first long sides, and in that from a cross-sectional view, the first long sides of the first conductive via have bottom segments higher than a top surface of the gate structure, (claim 11) polymer liners extend a first length along the first sides of the gate contact from the top view, the first sides of the gate contact extending a second length greater than the first length of the polymer liners, (claim 17) the source/drain contact wraps around at least three sides of the source/drain epitaxial structure and in contact with the isolation regions and in that, from a top view, the source/drain contact has two opposite first sides and two opposite second sides connecting the first sides, and the second sides are shorter than the first sides and more curved than the first sides, and (claim 19) in that the source/drain contact wraps around at least three sides of the source/drain epitaxial structure and in contact with the isolation regions, the gate contact having two opposite first sides and two opposite second sides connecting the first sides, and in that polymer liners are on the first sides of the gate contact and absent from the source/drain contact. Conclusion 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 11-23-2025 /TU-TU V HO/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Apr 03, 2024
Application Filed
Nov 23, 2025
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
99%
With Interview (+5.1%)
1y 12m
Median Time to Grant
Low
PTA Risk
Based on 1347 resolved cases by this examiner. Grant probability derived from career allow rate.

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