DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of Forming Semiconductor Device Including Vertical Transistor and Capacitor to Suppress Short-Channel Effects.
Election/Restrictions
Applicant’s election without traverse of Group II, the invention of a manufacturing method, in the reply filed on September 1, 2026, is acknowledged. Claims 1-18 have been cancelled, and claims 21-38 were added to the elected invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. US 2023/0029551 A1, hereinafter “H1”, in view of Sandhu et al. US 2008/0068876 A1, hereinafter “S1”.
Regarding independent claim 19, H1 discloses, A manufacturing method for a semiconductor device (semiconductor memory device H1, Fig 2), comprising: forming a BEOL structure (BEOL structure formed above substrate 201 in Fig 2 containing conductive contacts and memory-specific features); and forming a transistor on the BEOL structure (vertical transistors made of channels 133 and gates G1 and G2 in Fig 2), comprising: forming an active channel material (H1 [0079] channel structures deposited in S19 of Fig 5);
H1 does not disclose the method of forming a dummy wire on the active channel material; forming a spacer on a lateral surface of the dummy wire; removing the dummy wire to expose the active channel material; removing a portion of the active channel material, through the spacer, to form an active channel; removing the spacer; forming a metal gate to cover the active channel, wherein the metal gate is disposed adjacent to a lateral surface of the active channel; and planarizing the metal gate and the active channel, wherein the active channel has a first end surface, the metal gate has a first conductive surface, and the first end surface of the active channel protrudes relative to the first conductive surface of the metal gate.
However, S1, in the same field of endeavor, explicitly discloses a method of forming memory cells having reduce leakage current comprising; (S1 method shown in Figs 1-2) forming an active channel material (S1 Fig 1A, channel layer 103A);
forming a dummy wire on the active channel material (patternable material 105A);
forming a spacer on a lateral surface of the dummy wire (spacers 104A placed on the sides of 105A);
removing the dummy wire to expose the active channel material (between Figs 1A-1B, dummy material 105A is removed and layer 103B is exposed);
removing a portion of the active channel material, through the spacer, to form an active channel (Fig 1C, portion of 103A is removed to form channels 103C under remaining spacers 104C);
removing the spacer (Fig 2B, spacers on top of the vertical channels 203B are removed and replaced with drain/source regions 211B);
forming a metal gate(Fig 2B, gate conductor 208B is deposited) wherein the metal gate is disposed adjacent to a lateral surface of the active channel (in Fig 2B, gate conductor is placed on the sides of vertical channel structures),
and planarizing the metal gate and the active channel (the upper surfaces of the metal gate and active channel are planarized “using a chemical mechanical process as are known to those of ordinary skill in the art” [S1 Col 6 Line 43]), wherein the active channel has a first end surface (the first end surface, upper surface of the active channel 203B in S1 Fig 2B includes the upper surface of the drain/source regions 211B; this is similar to how the instant application defines “the first end 1211 of the active channel 121 may serve as one of the drain and the source of the transistor 120” [instant 0023]), the metal gate has a first conductive surface (the first conductive surface, upper surface of the metal gate includes the top surface of the gate conductor 208B), and the first end surface of the active channel protrudes (upper surface of 211B protrudes higher in the thickness direction (Z-direction, up the page)) relative to the first conductive surface of the metal gate (relative to the upper surface of 208B in Fig 2).
The method of forming the transistor structure as disclosed in S1 occurs on top of substrate (101A in S1 Fig 1A); the entire method of S1 therefore may be performed on the top surface of the bottom substrate in H1 (101 in Fig 2), so that the transistors may be disposed above the capacitors (209 in H1 Fig 2), with the top layer of S1’s transistor structure (Fig 2B, 211B and 209B) being disposed below the level of the bit line contacts (145 in H1 Fig 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the BEOL structure as disclosed in H1 with the method of forming a transistor as disclosed in S1, to form a transistor structure “such that no current flows across the channel region with zero gate bias voltage applied to gate conductor 208B” [S1 Col 6 line 35].
Regarding claim 20, H1 in view of S1 discloses, The manufacturing method as claimed in claim 19 (discussed above), wherein before forming the active channel material, the manufacturing method further comprises: forming a capacitor via (H1 discloses forming a capacitor contacts in S11 of Fig 5, which occurs before forming the active channel structures S19); wherein in forming the active channel material (H1 as modified by S1 to form the transistor structure with the method disclosed in S1 Figs 1-2), the active channel material is electrically connected with the capacitor via (H1 Fig 2, channel 133 is electrically connected to capacitor contact 103 [0008]); wherein after forming the metal gate and the active channel, the manufacturing method further comprises: forming a bit line via (H1 forms bit contacts and bit lines in steps S21-S23, Fig 5), wherein the bit line via (Fig 2 bit line contact 145), is electrically connected with the active channel (H1 [0082]), and the bit line via, the active channel and the capacitor via are stacked in a thickness direction of the semiconductor device (Fig 2, the vias and active channel are stacked in the Z-direction, up the page, similar to the instant application).
Regarding claim 21, H1 in view of S1 discloses, The manufacturing method as claimed in claim 19, wherein in removing the portion of the active channel material (S1 Fig 1A active channel material 103A) to form the active channel (removed in Fig 1C to form channels 103C), the active channel further has a first end surface (upper surface of upper region of channel, 211B S1 Fig 2B) and a second end surface (lower surface of channel 203B, S1 Fig 2B) opposite to the first end surface; in forming the metal gate (S1 Fig 2B gate 208B), the metal gate further has a second conductive surface (lower surface) opposite to the first conductive surface (upper surface); the second end surface of the active channel and the second conductive surface of the metal gate are flush (“flushed” in the instant application is defined as “substantially aligned” [instant 0022]; therefore, the lower surfaces of the active channel 203B and metal gate 208B are substantially aligned or flush in Fig 2B) with each other.
Regarding claim 22, H1 in view of S1 discloses The manufacturing method as claimed in claim 19, wherein forming the transistor on the BEOL structure (H1 Fig 2) further comprises: forming a capacitor via (H1 Fig 2 capacitor contact 103); wherein in removing the portion of the active channel material to form the active channel (occurs in the method of forming active channel as disclosed by S1 Figs 1-2), the active channel further has a first end surface (structures of H1 Fig 2 modified to have the structure and method of forming the active channel 203B in S1 Fig 2B; thereby replacing H1’s channel 133, and the top surface of the modified channel would be where 133T is labeled in H1 Fig 2) and a second end surface opposite to the first end surface (second end surface may be the lower end surface of the channel 133), and the second end surface of the active channel is connected to the capacitor via (H1 Fig 2, channel bottom surface 133B is in contact with 103 [0054]); wherein the manufacturing method further comprises (H1 method flowchart Fig 5): forming a bit line via (forming bit line contacts H1 Fig 5 S21), wherein the bit line via is connected with the first end surface (bit line contacts 145 H1 Fig 2, in contact with upper surface of channel 133T [0054]).
Regarding claim 23, H1 in view of S1 discloses The manufacturing method as claimed in claim 19 (H1 in view of S1), wherein in forming the bit line via (H1 Fig 5 S21), the active channel (formation of active channel as disclosed in S1) and the capacitor via (H1 Fig 5 S11) are stacked in a thickness direction of the semiconductor device (H1 Fig 2, elements are stacked in Z-direction, up the page, similar to the instant application).
Regarding claim 24, H1 in view of S1 discloses The manufacturing method as claimed in claim 19, wherein in forming the metal gate (formation of metal gate as disclosed in S1 into full BEOL structure as disclosed in H1), the active channel (H1 Fig 2 133) and the metal gate (H1 Fig 2 113b) overlap in an extension direction (X-direction, across the page) perpendicular to a thickness direction of the semiconductor device (X and Z-direction are perpendicular to each other).
Claim(s) 29-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over H1 in view of S1.
Regarding independent claim 29, H1 discloses A manufacturing method for a semiconductor device (memory device H1 Fig 2), comprising: forming a BEOL structure (Fig 2); however, H1 does not explicitly the method of forming a transistor on the BEOL structure comprising: forming an active channel; forming a metal gate, wherein the metal gate is disposed adjacent to a lateral surface of the active channel, the metal gate has a first conductive surface, and the active channel protrudes relative to the first conductive surface of the metal gate.
However, in the same field of endeavor, S1 discloses, forming a transistor on the BEOL structure (formation of transistor disclosed in the method of S1 Figs 1-2), comprising: forming an active channel (S1 active channel 203B); forming a metal gate (S1 Fig 2B 208B), wherein the metal gate is disposed adjacent to a lateral surface of the active channel (disposed laterally in Fig 2B), the metal gate has a first conductive surface (first conductive surface is upper conductive surface of 208B), and the active channel protrudes relative to the first conductive surface of the metal gate (S1’s active channel 203B includes the source/drain region 211B, similar to the instant application, and protrudes relative to the upper surface of the metal gate).
The method of forming the transistor structure as disclosed in S1 occurs on top of substrate (101A in S1 Fig 1A); the entire method of S1 therefore may be performed on the top surface of the bottom substrate in H1 (101 in Fig 2), so that the transistors may be disposed above the capacitors (209 in H1 Fig 2), with the top layer of S1’s transistor structure (Fig 2B, 211B and 209B) being disposed below the level of the bit line contacts (145 in H1 Fig 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the BEOL structure as disclosed in H1 with the specific method of forming a transistor as disclosed in S1, to form a transistor structure with a reduced amount of leakage current [S1 Col 6 line 35].
Regarding claim 30, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein forming the transistor on the BEOL structure further comprises (modifying H1 to create the transistors according to the method of S1): forming an active channel material (S1 active channel material 103A Fig 1B); and removing a portion of the active channel material to form the active channel (portion is removed between S1 Figs 1B and 1C to form channels 103C).
Regarding claim 31, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein before forming the active channel, the manufacturing method further comprises: forming a capacitor via (formation of capacitor contacts in H1 Fig 5 S11); wherein in forming the active channel, the active channel is electrically connected with the capacitor via (H1 Fig 2, active channels 133 are in electrical contact with capacitor contacts 103) ; wherein after forming the metal gate, the manufacturing method further comprises (H1 Fig 5): forming a bit line via (H1 Fig 2 145), wherein the bit line via, is electrically connected with the active channel (145 and 133 are in contact and electrically connected [0085]), and the bit line via, the active channel and the capacitor via are stacked in a thickness direction of the semiconductor device (H1 Fig 2, elements are stacked in Z-direction).
Regarding claim 32, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein in forming the active channel, the active channel further has a first end surface (upper surface of upper region of channel, 211B S1 Fig 2B) and a second end surface (lower surface of channel 203B, S1 Fig 2B) opposite to the first end surface; in forming the metal gate (S1 Fig 2B gate 208B), the metal gate further has a second conductive surface (lower surface) opposite to the first conductive surface (upper surface); the second end surface of the active channel and the second conductive surface of the metal gate are flush (“flushed” in the instant application is defined as “substantially aligned” [instant 0022]; therefore, the lower surfaces of the active channel 203B and metal gate 208B are substantially aligned or flush in Fig 2B) with each other.
Regarding claim 33, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein forming the transistor on the BEOL structure (H1 Fig 2) further comprises: forming a capacitor via (H1 Fig 5 S11); wherein in forming the active channel, the active channel further has a first end surface (H1 Fig 2 133T) and a second end surface (133B) opposite to the first end surface, and the second end surface of the active channel is connected to the capacitor via (133B is connected to 103); wherein the manufacturing method further (H1 Fig 5) comprises: forming a bit line via (S21), wherein the bit line via (Fig 2 145) is connected with the first end surface (bit line contacts 145 and 133T of active channel connect).
Regarding claim 34, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein in forming the bit line via (H1 Fig 2 145), the active channel (133) and the capacitor via (103) are stacked in a thickness direction of the semiconductor device (elements are stacked in the Z-direction, up the page in Fig 2).
Regarding claim 35, H1 in view of S1 discloses The manufacturing method as claimed in claim 29, wherein in forming the metal gate, the active channel and the metal gate overlap (S1 discloses method of forming the metal gate 208B laterally adjacent to channels 203B in Fig 2B, overlapping in the X-direction) in an extension direction (X-direction, across the page) perpendicular to a thickness direction (Z-direction, up the page) of the semiconductor device.
Claim(s) 36-38 is/are rejected under 35 U.S.C. 103 as being unpatentable over H1 in view of S1.
Regarding independent claim 36, H1 discloses A manufacturing method for a semiconductor device (memory device H1 Fig 2), comprising: forming a BEOL structure (Fig 2, structure of interconnects and memory elements with substrate 101); and forming a transistor on the BEOL structure (Fig 2 transistors made of channels 133 and gates G1 and G2), comprising: forming an active channel (H1 Fig 5, S19) ; forming a metal gate layer (S15), wherein the metal gate layer is disposed adjacent to a lateral surface of the active channel (shown in Fig 2); removing a portion of the metal gate layer to form a metal gate (S17 planarizing the gate electrode portions 113 to form gate electrodes 113b as shown in Figs 10-11); however, H1 does not disclose wherein the active channel has a first end surface, the metal gate has a first conductive surface, and the first end surface of the active channel protrudes relative to the first conductive surface of the metal gate.
However, in the same field of endeavor, S1 discloses wherein the active channel has a first end surface (the first end surface, upper surface of the active channel 203B in S1 Fig 2B includes the upper surface of the drain/source regions 211B; this is similar to how the instant application defines “the first end 1211 of the active channel 121 may serve as one of the drain and the source of the transistor 120” [instant 0023]), the metal gate has a first conductive surface (the first conductive surface, upper surface of the metal gate includes the top surface of the gate conductor 208B), and the first end surface of the active channel protrudes (upper surface of 211B protrudes higher in the thickness direction (Z-direction, up the page)) relative to the first conductive surface of the metal gate (relative to the upper surface of 208B in Fig 2).
Therefore, it would have been obvious to one having ordinary skill in the art to modify the transistor structure as disclosed in H1, to have a first end surface of the active channel protrude relative to the first conductive surface of the metal gate to reduce short-channel effects, thereby reducing leakage current [S1 Col 2 lines 35-38].
Regarding claim 37, H1 in view of S1 discloses The manufacturing method as claimed in claim 36, wherein forming the transistor on the BEOL structure (method of forming transistor disclosed in S1, on BEOL structure disclosed in H1 Fig 2) further comprises: forming an active channel material (S1 forms active channel material 103A in Fig 1A); and removing a portion of the active channel material to form the active channel (S1 etches away a portion of 103A to become active channels 103C in Fig 1C).
Regarding claim 38, H1 in view of S1 discloses The manufacturing method as claimed in claim 36 (the method of forming the H1 Fig 2 structure modified by the transistor formation method of S1), wherein before forming the active channel, the manufacturing method further comprises: forming a capacitor via (H1 Fig 5 S11); wherein in forming the active channel, the active channel is electrically connected with the capacitor via (H1 Fig 2, lower surface of active channel 133B is electrically connected to capacitor via 103 [H1 0008]); wherein after removing the portion of the metal gate layer to form the metal gate (after Fig 5 S17), the manufacturing method further comprises: forming a bit line via (S21), wherein the bit line via (Fig 2 145), is electrically connected with the active channel (Fig 2, upper surface of active channel 133T and bit contacts 145 are electrically connected [H1 0008]), and the bit line via, the active channel and the capacitor via are stacked in a thickness direction of the semiconductor device (Fig 2 elements stacked in Z-direction, up the page).
Claim(s) 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over H1 further in view of S1
Regarding claim 25, H1 in view of S1 discloses The manufacturing method as claimed in claim 19, and H1 does disclose forming a gate dielectric layer, but S1 more explicitly shows the method of forming the gate dielectric: further comprising: forming a gate dielectric layer (S1 Fig 2A gate dielectric 206A and insulator 207A); wherein in forming the metal gate (S1 Fig 2B, 208B), the gate dielectric layer (Fig 2B 207B) is disposed between the lateral surface of the active channel and the metal gate (S1 Fig 2B, the gate dielectric 207B is disposed between the lateral surface of 203B and 208B).
Therefore, it would have been obvious to further modify the BEOL structure as disclosed in H1 with the method of forming the gate dielectric disclosed in S1 Figs 1-2, to create a gate dielectric that fully isolates the active channel from the metal gate that exists according to the method of S1, providing a reduced leakage current [S1 Col 2 Para 2].
Claim(s) 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over H1 in view of S1 as applied to claim 25, further in view of Noh et al. US 2018/0204856 A1, hereinafter “N1”.
Regarding claim 26, H1 in view of S1 discloses The manufacturing method as claimed in claim 25 (described above); however, neither H1 nor S1 disclose: further comprising: forming an insulation layer, wherein the gate dielectric layer is disposed between insulation layer and the metal gate.
However, N1 discloses forming an insulation layer (N1 Fig 2, insulation layer 160), wherein the gate dielectric layer (N1's gate dielectric 142) is disposed between insulation layer and the metal gate (the dielectric layer 142 is between the gate 124 and insulation layer 160 in N1 Fig 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of forming a BEOL structure as disclosed in H1 and S1 to further have an additional insulation layer between the metal gate and any external electrodes, such as N1 Fig 2 second electrode 175. This layer increases the insulation between the gate metal and other conductors that may be in electrical contact with the active channel [N1 Col 7 Line 58].
Regarding claim 27, H1 in view of S1 and N1 discloses The manufacturing method as claimed in claim 26 (described above), wherein in forming the gate dielectric layer (formation of gate dielectric using the method described in S1, discussed for claim 25), the gate dielectric layer (S1 Fig 2B, 207B) comprises a first portion (vertical, in the thickness or Z-direction) and a second portion (horizontal, in the extension or X-direction); wherein in forming the metal gate, the first portion of the gate dielectric layer is disposed between the lateral surface of the active channel and a lateral surface of the metal gate (Fig 2B, 207B is between 203B and 208B lateral surfaces), and the second portion of the gate dielectric layer is disposed between an end surface of the insulation layer (H1 modified to include the insulation layer as disclosed in N1, N1 Fig 2 insulating layer 160) and an end surface of metal gate (N1’s Fig 2 discloses a gate dielectric with two portions, 142, between the inner end surface of the metal gates, 124, 121, and the end surface of the insulation layer 160. H1, modified to have the 2-portion gate dielectric layer as disclosed in S1, can be obviously modified to include an insulating layer in between the substrate 101 and dielectric layer 143 in H1 Fig 2, as discussed for claim 26 above, to increase insulation between conductive elements).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over H1 in view of S1 as applied to claim 19, further in view of Zhu et al. US 2023/0060149 A1, hereinafter “Z1”.
Regarding claim 28, H1 in view of S1 discloses, The manufacturing method as claimed in claim 19 (discussed above), further comprising: forming an insulation layer (H1 forms dielectric insulating layer 143), wherein the insulation layer covers the metal gate (layer 143 covers the gate 113B in H1 Fig 2B); however, neither H1 nor S1 disclose, forming a word line via, wherein the word line via passes through the insulation layer and is connected to the metal gate; and forming a word line, wherein the word line is connected to the word line via.
However, in the same field of endeavor, Z1 discloses a method of forming a vertical memory structure comprising: forming a word line via (Z1 Fig 7, word line contacts 627 [0078]), wherein the word line via passes through the insulation layer (word line via passes through the interlayer dielectric disposed on the metal gate lines, ILD in layer 616 [Z1 0075]) and is connected to the metal gate (627 connects to metal gate structures 634); and forming a word line (word lines 634 [0085]), wherein the word line is connected to the word line via (Z1 Fig 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the manufacturing method as disclosed in H1 and S1 to continue with the manufacturing of word line vias and word lines as disclosed in Z1 to create a functional memory devices with electrical connections to the word lines [Z1 0054].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Doornbos et al. US 2014/0061722 A1 which discloses a method of forming vertical transistors using dummy wires and spacers in Figs 1-19.
Nishi et al. US 2013/0126963 A1 which discloses a vertical transistor with an active channel laterally surrounded by a gate material and a gate dielectric with a vertical and horizontal portion in Figs 3-6.
Tsai et al. US 2022/0130832 A1 which discloses a vertical gate transistor with a plurality of channel structures coupled by the word line in Fig 23.
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/TERESA N MICKEY/Examiner, Art Unit 2897
/VU A VU/Primary Examiner, Art Unit 2897
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