DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 6-8, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim et al. (US 2021/0343617).
In reference to claim 1, Kim et al. (US 2021/0343617), hereafter “Kim,” discloses a semiconductor package, with reference to Figure 1, comprising:
a package substrate 15;
a lower chip 80 disposed on the package substrate;
an upper chip 25 disposed on the lower chip, paragraph 56;
an input/output signal bump 85 disposed between the lower chip and the package substrate, the input/output signal bump receives and outputs a signal to and from the lower chip, paragraph 58;
a wire bonding pad 34 disposed on an upper face of the upper chip, wherein a wire 68 is connected to the wire bonding pad, paragraph 55;
a first input/output signal ball disposed on a lower face of the package substrate, the first input/output signal ball receives and outputs the signal to and from the lower chip, the first input/output signal ball is connected to the input/output signal bump; and
a second input/output signal ball disposed on the lower face of the package substrate, the second input/output signal ball receives and outputs a signal to and from the upper chip, the second input/output signal ball is electrically connected to the wire bonding pad,
wherein the first input/output signal ball and the second input/output signal ball are spaced apart from each other in a first direction, the input/output signal bump is disposed closer to the first input/output signal ball than the second input/output signal ball, and
[AltContent: textbox (First side wall)][AltContent: arrow] the wire bonding pad is disposed closer to the second input/output signal ball than the first input/output signal ball in the first direction, see annotated Figure 1 below.
In reference to claim 3, Kim discloses an adhesive layer 91 disposed between the lower chip and the upper chip, paragraph 59.
In reference to claim 6, Kim discloses a redistribution layer, 53 in Figure 3, disposed on the upper face of the upper chip 25, the redistribution layer is connected to the wire bonding pad 34, paragraph 43.
In reference to claim 7, Kim discloses an extending length of the redistribution layer, 53 in Figure 3, in the first direction (horizontal direction in Figure 3) is greater than an extending length of the wire bonding pad 34 in the first direction.
In reference to claim 8, Kim discloses a width of the wire bonding pad, 34 in Figure 3, in a second direction (vertical direction in Figure 3) intersecting the first direction is greater than a width of the redistribution layer 53 in the second direction.
In reference to claim 10, Kim discloses the lower chip and the upper chip include a first side wall and a second side wall opposite to each other in the first direction; the wire bonding pad is closer to the first side wall than the second side wall; and the input/output signal bump is closer to the second side wall than the first side wall.
In reference to claim 11, Kim discloses a molding film 71 disposed on the package substrate, the molding film covers the lower chip and the upper chip, paragraph 60.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Pachamuthu et al. (US 2019/0067034).
In reference to claim 2, Kim does not disclose the lower chip has a same width as the upper chip in the first direction.
Pachamuthu et al. (US 2019/0067034) discloses an analogous semiconductor chip package including teaching the lower chip, 410 in Figure 4A, has a same width as the upper chip 420 in the first direction. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the lower chip has a same width as the upper chip in the first direction. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one chip size for another.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Lee et al. (US 2024/0145422).
In reference to claim 4, Kim is silent regarding a power ball disposed on the lower face of the package substrate, the power ball is spaced apart from the first input/output signal ball and the second input/output signal ball in the first direction; and a power bump disposed between the lower chip and the package substrate, the power bump is spaced apart from the input/output signal bump in the first direction and is electrically connected to the power ball.
Lee et al. (US 2024/0145422), hereafter “Lee,” discloses an analogous semiconductor chip package including teaching a power ball, solder ball (unlabeled) of substrate 106 in Figure 1, disposed on the lower face of the package substrate, the power ball is spaced apart from the first input/output signal ball and the second input/output signal ball in the first direction; and a power bump, 110 disposed between the lower chip 102 and the package substrate 106, the power bump is spaced apart from the input/output signal bump in the first direction and is electrically connected to the power ball, paragraph 11.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a power ball to be disposed on the lower face of the package substrate, the power ball is spaced apart from the first input/output signal ball and the second input/output signal ball in the first direction; and a power bump disposed between the lower chip and the package substrate, the power bump is spaced apart from the input/output signal bump in the first direction and is electrically connected to the power ball.
One would have been motivated to do so in order to provide electrical power and logic control to the semiconductor chips in the package, id.
In reference to claim 5, Kim in view of Lee is silent regarding a level of a signal provided to the power ball is greater than a level of a signal provided to the first input/output signal ball and the second input/output signal ball.
The examiner takes OFFICIAL NOTICE that it is well known in the art for power voltage levels to be higher than signal voltage levels. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a level of a signal provided to the power ball to be greater than a level of a signal provided to the first input/output signal ball and the second input/output signal ball. One would have been motivated to do so in order to provide electrical power and logic control to the semiconductor chips in the package, as suggested by Lee paragraph 11.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Nishioka (US 2004/0075176).
In reference to claim 9, Kim discloses an input/output bump pad, 82 in Figure 1, disposed on a lower face of the lower chip, the input/output bump pad faces the package substrate and is in direct contact with the input/output signal bump 85, paragraphs 56 and 58.
Kim does not disclose wherein a width of the wire bonding pad in the first direction is greater than a width of the input/output bump pad in the first direction.
Nishioka (US 2004/0075176) discloses an analogous semiconductor chip package including teaching a width of a wire bonding pad in the first direction is greater than a width of an input/output bump pad in the first direction, paragraph 21. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a width of the wire bonding pad in the first direction to be greater than a width of the input/output bump pad in the first direction. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the relative pad sizes taught by Nishioka to the package of Kim.
Claims 12, 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Kosaka (US 2020/0075543).
In reference to claim 12, Kim discloses a semiconductor package, with reference to Figure 1, comprising:
a package substrate 15;
a first semiconductor chip stack disposed on the package substrate, the first semiconductor chip stack including a first lower chip 80 and a first upper chip 25 sequentially stacked, paragraph 56;
a first wire bonding pad 34 disposed on the first upper chip, the first wire bonding pad is electrically connected to the package substrate by a wire 68, paragraph 55; and
an input/output signal bump 85 disposed between the first semiconductor chip stack and the package substrate, the input/output signal bump receives and outputs input/output signals to and from the first lower chip, paragraph 58,
wherein the package substrate includes a first input/output signal ball 94 disposed on a lower face of the package substrate, the first input/output signal ball is electrically connected to the input/output signal bump, paragraph 62,
wherein the package substrate further includes a second input/output signal ball 94 disposed on the lower face of the package substrate and spaced apart from the first input/output signal ball, the second input/output signal ball is electrically connected to the wire,
the first semiconductor chip stack includes a first side face and a second side face opposite to the first side face,
the first input/output signal ball is disposed closer to the first side face than the second side face, and
the second input/output signal ball is disposed closer to the second side face than the first side face, see annotated Figure 1 above (as shown in reference to Figure 1).
Kim does not disclose a second semiconductor chip stack disposed on the package substrate and spaced apart from the first semiconductor chip stack, the second semiconductor chip stack including a second lower chip and a second upper chip sequentially stacked;
the first semiconductor chip stack includes a first side face facing the second semiconductor chip stack.
Kosaka (US 2020/0075543), hereafter “Kosaka,” discloses an analogous semiconductor chip stack package including teaching a package substrate, 11 in Figure 2,
a first semiconductor chip stack 12 disposed on the package substrate, a second semiconductor chip stack 14 disposed on the package substrate and spaced apart from the first semiconductor chip stack, the second semiconductor chip stack including a second lower chip and a second upper chip sequentially stacked;
the first semiconductor chip stack includes a first side face facing the second semiconductor chip stack, paragraph 20.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the package to include a second semiconductor chip stack disposed on the package substrate and spaced apart from the first semiconductor chip stack, the second semiconductor chip stack including a second lower chip and a second upper chip sequentially stacked;
the first semiconductor chip stack includes a first side face facing the second semiconductor chip stack.
One would have been motivated to do so in order to provide additional chips in a single package, as suggested by Kosaka paragraph 4.
In reference to claim 13, Kim discloses an adhesive layer 91 disposed between the first lower chip and the first upper chip, paragraph 59.
In reference to claim 15, Kim discloses a distance between the second side face and the first wire bonding pad is less than a distance between the second side face and the input/output signal bump, see annotated Figure 1 above.
In reference to claim 16, Kim discloses the input/output signal bump is disposed closer to the first side face than the second side face; and the first wire bonding pad is disposed closer to the second side face than the first side face, see annotated Figure 1 above.
In reference to claim 17, Kosaka discloses a molding film, 18 in Figure 2, disposed on the package substrate, the molding film covers the first semiconductor chip stack and the second semiconductor chip stack, paragraph 20, similar to 71 in Figure 1 of Kim, paragraph 60.
Claims 14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Kosaka (US 2020/0075543) and Lee et al. (US 2024/0145422).
In reference to claim 14, Kim discloses a second wire bonding pad, 34 in Figure 3, disposed on the first upper chip and spaced apart from the first wire bonding pad.
Kim is silent regarding a power ball disposed on the lower face of the package substrate, the power ball provides power to the first lower chip or the first upper chip; a power bump disposed between the first semiconductor chip stack and the package substrate, the power bump is electrically connected to the power ball; and the second wire bonding pad is electrically connected to the power ball.
Lee teaches a power ball, solder ball (unlabeled) of substrate 106 in Figure 1, disposed on the lower face of the package substrate 106, the power ball provides power to the first lower chip or the first upper chip; a power bump 110 disposed between the first semiconductor chip stack and the package substrate, the power bump is electrically connected to the power ball, paragraph 11; and the second wire bonding pad is electrically connected to the power ball, paragraph 11.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a power ball to be disposed on the lower face of the package substrate, the power ball provides power to the first lower chip or the first upper chip; a power bump to be disposed between the first semiconductor chip stack and the package substrate, the power bump is electrically connected to the power ball; and the second wire bonding pad to be electrically connected to the power ball.
One would have been motivated to do so in order to provide electrical power and logic control to the semiconductor chips in the package, as suggested by Lee paragraph 11.
In reference to claim 18, Kim discloses a semiconductor package, with reference to Figure 1, comprising:
a package substrate 15;
a first semiconductor chip stack disposed on the package substrate, the first semiconductor chip stack including a first lower chip 80 and a first upper chip 25 sequentially stacked, paragraph 56;
a first wire bonding pad 34 disposed on the first upper chip, the first wire bonding pad is electrically connected to the package substrate by a first wire 68, paragraph 55;
a first input/output signal bump 85 disposed between the first semiconductor chip stack and the package substrate, the first input/output signal bump receives and outputs an input/output signal to and from the first lower chip, paragraph 58;
a first input/output signal ball 94 disposed on a lower face of the package substrate, the first input/output signal ball is connected to the first input/output signal bump;
a second input/output signal ball 94 disposed on the lower face of the package substrate, the second input/output signal ball is connected to the first wire bonding pad, see annotated Figure 1 above (as shown in reference to claim 1).
Alternatively, Kim discloses a second semiconductor chip stack disposed on the package substrate, the second semiconductor chip stack including a second lower chip 80 and a second upper chip 25 sequentially stacked, paragraph 56;
a second wire bonding pad 34 disposed on the second upper chip, the second wire bonding pad is electrically connected to the package substrate by a second wire 68, paragraph 55;
a second input/output signal bump 85 disposed between the second semiconductor chip stack and the package substrate, the second input/output signal bump receives and outputs an input/output signal to and from the second lower chip, paragraph 58;
a third input/output signal ball 94 disposed on a lower face of the package substrate, the third input/output signal ball is connected to the second input/output signal bump;
a fourth input/output signal ball 94 disposed on the lower face of the package substrate, the fourth input/output signal ball is connected to the second wire bonding pad, see annotated Figure 1 below.
[AltContent: textbox (Second wire bonding pad)][AltContent: arrow]
Kim does not disclose a second semiconductor chip stack disposed on the package substrate and spaced apart from the first semiconductor chip stack,
a power ball disposed on the lower face of the package substrate, the power ball provides power to the first semiconductor chip stack or the second semiconductor chip stack, or
wherein a distance between the first input/output signal bump and the second input/output signal bump is less than a distance between the first wire bonding pad and the second wire bonding pad.
Kosaka discloses an analogous semiconductor chip stack package including teaching a package substrate, 11 in Figure 2,
a first semiconductor chip stack 12 disposed on the package substrate, a second semiconductor chip stack 14 disposed on the package substrate and spaced apart from the first semiconductor chip stack, the second semiconductor chip stack including a second lower chip and a second upper chip sequentially stacked, paragraph 20.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention, in view of Kosaka, to duplicate the chip stack of Kim such that the package includes a second semiconductor chip stack disposed on the package substrate and spaced apart from the first semiconductor chip stack, the second semiconductor chip stack including a second lower chip and a second upper chip sequentially stacked;
a second wire bonding pad disposed on the second upper chip, the second wire bonding pad is electrically connected to the package substrate by a second wire;
a second input/output signal bump disposed between the second semiconductor chip stack and the package substrate, the second input/output signal bump receives and outputs an input/output signal to and from the second lower chip;
a third input/output signal ball disposed on a lower face of the package substrate, the third input/output signal ball is connected to the second input/output signal bump;
a fourth input/output signal ball disposed on the lower face of the package substrate, the fourth input/output signal ball is connected to the second wire bonding pad
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case duplicating the chip stack of Kim, as suggested by Kosaka, in order to provide additional chips in a single package, Kosaka paragraphs 4, 24, and 41.
[AltContent: textbox (One same package
↔)]In reference to a distance between the first input/output signal bump and the second input/output signal bump being less than a distance between the first wire bonding pad and the second wire bonding pad, this naturally results from the combination of Kim and Kosaka to duplicate the chip stack of Kim in the same package, as seen by the first input/output signal bump and the second input/output signal bump and the first wire bonding pad and the second wire bonding pad in the annotated figures below.
Kosaka does not disclose a power ball disposed on the lower face of the package substrate, the power ball provides power to the first semiconductor chip stack or the second semiconductor chip stack.
Lee discloses an analogous semiconductor chip package including teaching a power ball, solder ball (unlabeled) of substrate 106 in Figure 1, disposed on the lower face of the package substrate, the power ball provides power to the first semiconductor chip stack or the second semiconductor chip stack, paragraph 11.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a power ball to be disposed on the lower face of the package substrate, the power ball provides power to the first semiconductor chip stack or the second semiconductor chip stack. One would have been motivated to do so in order to provide electrical power and logic control to the semiconductor chips in the package, id.
In reference to claim 19, Kim in view of Kosaka discloses a distance between the first input/output signal ball and the third input/output signal ball is less than a distance between the second input/output signal ball and the fourth input/output signal ball, see annotated Figure above in reference to claim 18.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0343617) in view of Kosaka (US 2020/0075543) and Lee et al. (US 2024/0145422) as applied to claim 18 above and further in view of Kim et al. (US 2021/0242101).
In reference to claim 20, Kim does not disclose the first semiconductor chip stack includes a field programmable gate array (FPGA).
Kim et al. (US 2021/0242101) discloses an analogous semiconductor chip package including teaching the first semiconductor chip stack includes a field programmable gate array (FPGA)Paragraph 28. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first semiconductor chip stack includes a field programmable gate array (FPGA).To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the packaging technique of Kim to the FPGA device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kwon et al. (US 2015/0014862), Kim et al. (US 2020/0020637), and Hoffman et al. (US 6,737,750) disclose related semiconductor chip stack packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
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