DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 4th, 2024, is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, Claim 2 recites the limitation “the forming the substrate” in line 1. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, claim 2 has been interpreted as follows based on Claim 1 and paragraph [0067] of the instant specification:
Claim 2: The method of claim 1, wherein the preparing the substrate further comprises: forming a first base substrate on a carrier substrate; forming the metal pattern on the first base substrate; and forming a second base substrate on the first base substrate and the metal pattern.
Regarding Claims 3-6, Claims 3-6 all ultimately depend from Claim 2 and do not resolve the indefiniteness; therefore, they are rejected for the same reasons as Claim 2 due to their dependence therefrom.
Regarding Claim 8, one of ordinary skill in the art would not be able to determine the scope of the claimed subject matter as written, specifically wherein an etch rate of the first insulating layer, an etch rate of the second insulating layer, and an etch rate of the inter-insulating layer are smaller than an etch rate of the etch stop pattern (emphasis added in bold).
While the claim as written derives support from paragraphs [0014, 00115, 00174] of the specification, one of ordinary skill in the art would understand that from the plain meaning of the verbiage in the claim and specification as written, it would be impossible to determine the scope of the claimed invention. See relevant prior art in the same field of etching and display devices in Yoon et al., US PGPub 2015/0372070 A1, specifically in paragraph [0121] of Yoon et al.: “the etch stop layer 103 protects layers under the etch stop layer 103 when forming the second insulating layer ILD2” and “the etching rate of the etch stop layer 103 is different from the etching rate of the first insulating layer ILD1. For example, the etching rate of the etch stop layer 103 may be lower than the etching rate of the first insulating layer ILD1.” See also a relevant textbook for etching that would be known to one of ordinary skill in the art, providing a definition for etch selectivity which adds further context, “A ratio of etch rates (ER1/ER2) between the etch target film and the underlying film and a ratio of etch rates (ER1/ER3) between the etch target film and the mask are called the selectivity to the underlying film and the selectivity to the mask, respectively. These are parameters that indicate how much the underlying film and mask are etched as the etch target film is etched” Nojiri, Kazuo. Dry Etching Technology for Semiconductors. 1st ed. 2015., Springer International Publishing, 2015, Chapter 1.2.
The prior art contains working examples wherein the etch rate of an etch stop is smaller than the etch rate of target film, that is, when the etch stop is exposed during etching of the target film, there is, by design, little to no etching of the etch stop. With such established knowledge, a person of ordinary skill in the art before the effective filing date of the claimed invention would struggle to determine the scope of the claimed invention, resulting in doubt and problems of indefiniteness such as, “in what step do these different etch rates occur” and “in which etches and etchants” and “if the etch stop pattern is in service to formation of multiple contact holes, at which point in the claimed method must the pattern’s etch rate be smaller than an etch rate of the insulating layers?”
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Indeed, even from the specification in paragraphs [00177-00179, 00184] and in FIGs. 17-18 it is clear that the purpose of the etch stop pattern in the instant application is consistent with the plain meaning and knowledge of one of ordinary skill in the art (providing protection to the layers beneath it for the purposes of multiple contact hole formation—see specifically FIG. 18, wherein during formation of contact hole OS3 extended to OS2, damage and unwanted etching of insulating layers in the red outline is prevented by the etch stop pattern ES). As written, however, the scope of claim 8 is unclear in light of such a conflict of information ([0014, 0015, 00174] vs [00177-00179, 00184], FIGs. 17-18, and cited relevant prior art above). Therefore, a person of ordinary skill in the art would be unable to interpret the scope of the claimed subject matter as written and so Claim 8 is rejected for being indefinite.
However, for examination purposes, the Examiner makes the assumption that the claim as written is due to translation error of the foreign priority document and has given the claim the interpretation consistent with the purpose and goal of the claimed invention, the plain meaning given to such terms as etch rate and etch stop patterns, and the knowledge of one of ordinary skill in the art before the effective filing date of the invention as evidenced by the provided references. Therefore, Claim 8 has been interpreted as follows:
Claim 8: The method of claim 7, wherein an etch rate of the first insulating layer, an etch rate of the second insulating layer, and an etch rate of the inter-insulating layer are greater than an etch rate of the etch stop pattern.
Regarding Claim 9, as Claim 9 depends directly from Claim 8 and does not resolve the indefiniteness, it too is rejected for the same reasons as Claim 8 due to its dependence therefrom and is interpreted for continuity and understandability as follows:
Claim 9: The method of claim 8, wherein when each of the first insulating layer, the second insulating layer, and the inter-insulating layer includes an inorganic material, an etch selectivity between at least one of the first insulating layer, the second insulating layer and the inter-insulating layer including the inorganic material and the etch stop pattern is about 15:1 or more.
Regarding Claim 10, while the Examiner does make the assumption, as stated above with respect to Claims 8 and 9, that a translation error or similar is the issue source of the indefiniteness, a further problem stems from the limitation that the etch selectivity between the insulating layers and the etch stop pattern be about 1:1000 or more (interpreted as about 1000:1 or more as explained above).
The specification and claim are silent on etchants, etch process, or indeed any type of disclosure or discussion of how an etch would be carried out such that a massively selective etch would be achieved. Rather, the only mention or regard given to the claimed etch selectivity is in paragraphs [0016, 00117, 00176] of the specification and amount to nothing more than a declarative statement that it be so.
Therefore, as there is significant doubt that a person of ordinary skill in the art would be able to determine the scope of the claimed subject matter as written and as supported in the specification, Claim 10 is rejected for indefiniteness.
Although assumed interpretations of the claims have been provided for purposes of examination, the Examiner provides the following caveat as a reminder to the Applicant: any potential amendments to alter the claim language must be done carefully and in full understanding of the possibility of 112(a) written description rejections upon updating the claim language to limitations unsupported (i.e., new matter) by the originally filed specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7, and 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US PGPub 2021/0050398 A1 (hereinafter referred to as Kim), in view of Cha et al., US Patent No. 10826026 B2 (hereinafter referred to as Cha).
Regarding Claim 1, Kim discloses a manufacturing method of a display device (FIG. 5, S01-S12; FIG. 24, display device 1_3), the method comprising:
preparing a substrate (FIG. 24, base substrate 101) which includes a metal pattern (FIG. 24, light-shielding pattern 122; [0115, 0117]) and in which a display area (FIG. 24, display region DA; [0098]) and a non-display area are defined (FIG. 24, non-display region NDA, [0098]);
forming a first active pattern disposed on the substrate (FIG. 24, silicon transistor region AR1; [0101]) and including a first area (FIG. 24, source/drain region 105a; [0110]), a second area (FIG. 24, source/drain region 105b; [0110]), and a first channel area disposed between the first area and the second area (FIG. 24, channel region 105c; [0110]);
forming a first gate electrode pattern overlapping the first channel area on the first active pattern (FIG. 24, first gate electrode 121; [0110]);
forming a second active pattern on the first gate electrode pattern (FIG. 24, oxide transistor region AR2; [0101]);
forming an etch stop pattern in a same layer as the second active pattern (Kim FIG. 24, etch stop pattern 137_3; [0202-0207])
However, Kim does not disclose and overlapping the first area and the second area of the first active pattern.
In analogous art, Cha teaches a similar method for manufacturing a display device comprising: forming an etch stop pattern in a same layer as the second active pattern and overlapping the first area and the second area of the first active pattern; (Cha FIGs. 4, 5, etch prevention layer 51a, first and second electrodes (source and drain electrodes) S1, D1; Col 10, lines 7-11, Col 15 lines 15-27). Kim and Cha both make use of etch stop patterns for protections of lower layers, i.e., using etch stop patterns to prevent etching of any layers underneath such patterns when forming contact holes (Kim paragraphs [0202-0207]; Cha Col 15 lines 15-27).
Cha teaches using these etch stop patterns in the first and second areas of the active pattern (where the first and second electrodes will be, as seen in FIG. 4; Col 12 lines 27-43, Col 15 lines 15-27) for the benefit of such patterns allowing simultaneous contact hole formation in order to reduce manufacturing costs, as “the contact holes may be formed by using one photomask, and a manufacturing cost may be reduced compared to other cases in which contact holes formed in different insulation layers are formed by using different photomasks, respectively” (Col 17 lines 13-17).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the etch stop pattern of Kim to further overlap and cover the first and second areas as taught in Cha for the known and predictable result of preventing unwanted etching of the first and second areas of the active patterns during simultaneous contact hole formation for the benefits taught in Cha of reduced manufacturing costs (Col 16 lines 66-67, Col 17 lines 1-35).
Cha further discloses forming an inter-insulating layer covering the etch stop pattern (FIG. 5, inter-insulating layer 160, Col 13 lines 4-22, Col 5 lines 58-67);
defining a first hole exposing the etch stop pattern (FIG. 8, R2/511, etch stop pattern 51a; Col 15 lines 64-67, Col 16 lines 1-26) and a second hole exposing the inter-insulating layer (FIG. 8, R3/521, inter-insulating layer 160; Col 15 lines 64-67, Col 16 lines 1-26);
defining a third hole extended to the second hole and exposing a top surface of the substrate (FIG. 9, R3/522, buffer layer 112; Col 16 lines 27-38);
defining a fourth hole extended to the first hole and penetrating the etch stop pattern (FIG. 10, R2/51, etch stop pattern 51a; Col 16 lines 39-55) and a fifth hole extended to the third hole and exposing the metal pattern (FIG. 10, R3/52, lower electrode 31; Col 16 lines 39-55);
forming a metal pattern connection electrode disposed on the metal pattern and connected to the metal pattern through the fifth hole (FIG. 5, data conductor 74, lower electrode 31, contact hole 52; Col 15 lines 56-65); and
forming a light-emitting device on the metal pattern connection electrode (FIG. 5, OLED 710, 720, 730; Col 15 lines 56-65).
As stated above, Cha teaches a method for manufacturing a display device which reduces manufacturing costs by enabling simultaneous contact hole formation, i.e., using one photomask for multiple contact holes. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim with the teachings of Cha, defining multiple contact holes simultaneously as disclosed above, for the benefits of reduced manufacturing costs (Col 16 lines 66-67, Col 17 lines 1-35).
Regarding Claim 2, Kim in view of Cha discloses the method of claim 1 as discussed above.
Cha further discloses wherein the forming the substrate comprising: forming a first base substrate (FIG. 6, barrier layer 111) on a carrier substrate (FIG. 6substrate 110; Col 15 lines 34-47);
forming the metal pattern (FIG. 6, lower electrode 31) on the first base substrate (FIG. 6, barrier layer 111; Col 15 lines 34-47); and
forming a second base substrate (FIG. 6, buffer layer 112) on the first base substrate (FIG. 6, barrier layer 111) and the metal pattern (FIG. 6, lower electrode 31; Col 15 lines 34-47).
Regarding Claim 3, Kim in view of Cha discloses the method of claim 2 as discussed above.
Cha further discloses wherein the third hole (FIG. 9, R3/522) exposes a top surface of the second base substrate (FIG. 9, buffer layer 112; Col 16 lines 27-38).
Regarding Claim 4, Kim in view of Cha discloses the method of claim 2 as disclosed above.
Cha further discloses wherein the first base substrate (FIG. 6, barrier layer 111) and the second base substrate (FIG. 6, buffer layer 112) include plastic with flexible characteristics (Col 11 lines 10-14).
Regarding Claim 5, Kim in view of Cha discloses the method of claim 4 as discussed above.
Cha further discloses wherein the first base substrate (FIG. 6, barrier layer 111) and the second base substrate (FIG. 6, buffer layer 112) include polyimide (Col 11 lines 10-14).
Regarding Claim 7, Kim in view of Cha discloses the method of claim 1 as discussed above.
Kim further discloses further comprising:
forming a first insulating layer covering the first active pattern after the forming the first active pattern (FIG. 7, first gate insulating film GI1; [0112]); and
forming a second insulating layer covering the first gate electrode pattern after the forming the first gate electrode pattern (FIG. 9, first interlayer insulating film ILD1; [0119]).
Regarding Claim 11, Kim in view of Cha discloses the method of claim 1 as discussed above.
Kim further discloses wherein the first active pattern (FIG. 24, silicon transistor region AR1) and the second active pattern (FIG. 24, oxide transistor region AR2) include different materials from each other (FIG. 24; [0101]).
Regarding Claim 12, Kim in view of Cha discloses the method of claim 1 as discussed above.
Kim further discloses wherein the first active pattern includes a silicon semiconductor (FIG. 24, silicon transistor region AR1 and silicon semiconductor layer 105; [0101, 0108-0109]).
Regarding Claim 13, Kim in view of Cha discloses the method of claim 1 as discussed above.
Kim further discloses wherein the etch stop pattern (FIG. 24, etch stop pattern 137_3) and the second active pattern are formed simultaneously (FIG. 24, oxide semiconductor layer 135; [0202-0207]).
Regarding Claim 14, Kim in view of Cha discloses the method of claim 13 as discussed above.
Kim further discloses wherein the etch stop pattern (FIG. 24, etch stop pattern 137_3) and the second active pattern (FIG. 24, oxide semiconductor layer 135) includes a same oxide semiconductor ([0207]).
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Regarding Claim 15, Kim in view of Cha discloses the method of claim 14 as discussed above.
Kim further discloses wherein the etch stop pattern (FIG. 24, etch stop pattern 137_3) and the second active pattern (FIG. 24, oxide semiconductor layer 135) includes indium-gallium-zinc-oxide (“IGZO”) ([0120, 0207]).
Regarding Claim 16, Kim in view of Cha discloses the method of claim 1 as discussed above.
Cha further discloses wherein the fifth hole (FIG. 5, R3/522) is defining in the display area (FIG. 4, 5, see annotated figure below highlighting line V-V’ along which FIG. 5 shows the respective cross-section, showing clearly that the fifth hole would be in the pixel area PX; Col 10 lines 40-45).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cha as applied to claim 2 above, and further in view of Chen et al., US PGPub 2014/0375916 A1 (hereinafter referred to as Chen).
Regarding Claim 6, Kim in view of Cha discloses the method of claim 2 as discussed above.
However, neither Kim nor Cha disclose further comprising: removing the carrier substrate after the forming the light-emitting device.
In analogous art, Chen is directed to a similar method for manufacturing a flexible display device with multiple substrate layers. Chen discloses the method of manufacturing the display device further comprising: removing the carrier substrate (FIG. 1H, carrier substrate 110) after the forming the light-emitting device (FIG. 1H, display device 190; [0045-0047]).
Chen teaches that the carrier substrate should be removed after forming the light-emitting device for the benefits of improved manufacturing yield, “since the active element 140 and the pad 150 are fabricated on the buffer layer 120 and the buffer layer 120 is separated from the carrier substrate 110 through the laser lift-off process, issues such as the adhesive force and the stress between the flexible substrate and the carrier substrate can be neglected during release, and the occurrences of crack or disconnection due to the stress can be avoided, thereby further enhancing the manufacturing yield of the flexible display panel 100” [0050].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method as taught by Kim in view of Cha further with the teachings of Chen to remove the carrier substrate after forming the light-emitting device for the stated benefit of increased manufacturing yield by reducing cracking or disconnection due to stress.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cha as applied to claim 7 above, and further in view of Cho et al., US PGPub 2021/0376243 A1 (hereinafter referred to as Cho).
Regarding Claim 8, Kim in view of Cha discloses the method of claim 7 as discussed above.
However, neither Kim nor Cha disclose wherein an etch rate of the first insulating layer, an etch rate of the second insulating layer, and an etch rate of the inter-insulating layer are smaller than an etch rate of the etch stop pattern.
In analogous art, Cho is directed to a method of manufacturing an organic light-emitting display device. Cho discloses a method wherein an etch rate of the first insulating layer (FIGs. 29-31, buffer layer 120), an etch rate of the second insulating layer (FIGs. 29-31, first interlayer insulating film 170a), and an etch rate of the inter-insulating layer (FIGs. 29-31, second interlayer insulating film 170b) are smaller than an etch rate of the etch stop pattern (FIGs. 29-31, semiconductor layer 130; [0103-0104, 0119, 0120-0121]). As stated above in the 112(a) rejection: ‘smaller’ is being interpreted as ‘greater’ here.
Cho teaches multiple insulating layers formed on a layer of IGZO, i.e., a layer not to be damaged or etched during patterning of the insulating films ([0103-0104]), wherein the etch rate of each of the insulating layers is greater than the etch rate of the layer not-to-be-etched, i.e., the layer of IGZO, i.e., the “etch stop pattern”. This is for the stated benefit of preventing damage “during the formation of the second contact holes” ([0104]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim in view of Cha with the etch rate teachings of Cho such that the insulating layers have a greater etch rate than the etch stop pattern for the benefit of preventing any deterioration during contact hole formation ([0104]).
Regarding Claim 9, Kim in view of Cha in further view of Cho disclose the method of claim 8 as discussed above.
Cho further discloses wherein when each of the first insulating layer (FIGs. 29-31, buffer layer 120), the second insulating layer (FIGs. 29-31, first interlayer insulating film 170a), and the inter-insulating layer (FIGs. 29-31, second interlayer insulating film 170b) includes an inorganic material ([0119]), an etch selectivity between at least one of the first insulating layer, the second insulating layer and the inter-insulating layer including the inorganic material and the etch stop pattern is about 1:15 or more ([0026, 0119-0121]). As stated above in the 112(a) rejection: ‘1:15’ is being interpreted as ’15:1’ here.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cha as applied to claim 1 above, and further in view of Ryu et al., US Patent No. 11152435 B2 (hereinafter referred to as Ryu).
Regarding Claim 17, Kim in view of Cha disclose the method of claim 1 as discussed above.
However, neither Kim nor Cha disclose wherein the fifth hole is defining in the non-display area.
In analogous art, Ryu is directed to a display device and discloses wherein the fifth hole (FIGs. 9, 10, second power line PL2 connected to light-blocking conductive layer CP through contact hole CH) is defining in the non-display area (FIGs. 9, 10, non-display area NDA).
Ryu teaches that having a connection between the metal pattern (light-blocking conductive layer CP) through the fifth hole (contact hole CH) in the non-display area (non-display area NDA) would be beneficial, as it offers additional ways of “[receiving] power (or signal) transmitted to the one power line” (Col 19 line 30) and controlling “the amount of current flowing through the light emitting element OLED connected to the transistor T” (Col 19 lines 8-21).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim in view of Cha with the teachings of Ryu to place the fifth hole through which a metal connection electrode is connected to a metal pattern in the non-display area for the benefit of improved power-and-signal transmission redundancy and OLED light-emission control (Col 19 lines 8-21, line 30).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yoon et al., US PGPub 2015/0372070 A1, which, as discussed above, is directed to a display device which uses an etch stop layer to facilitate contact hole formation.
Nojiri, Kazuo. Dry Etching Technology for Semiconductors. 1st ed. 2015., Springer International Publishing, 2015, Chapter 1.2, which, as discussed above, is a relevant textbook chapter which provides a plain language definition for etch rate and etch selectivity.
Yun et al., US PGPub 2022/0199729 A1, which is directed to a manufacturing method for a flexible display device containing a similar structure and simultaneous contact hole formation.
Zhao et al., US PGPub 2023/0387134, which is directed to a manufacturing method for a display device containing a similar structure and contact hole formation with use of etch stop patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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