Prosecution Insights
Last updated: October 02, 2026
Application No. 18/626,549

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Non-Final OA §103
Filed
Apr 04, 2024
Priority
Sep 19, 2023 — TW 112135768
Examiner
VALENZUELA, PATRICIA D
Art Unit
Tech Center
Assignee
Taiwan-Asia Semiconductor Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
652 granted / 722 resolved
+30.3% vs TC avg
Minimal +2% lift
Without
With
+2.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
82 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
68.2%
+28.2% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
6.2%
-33.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 722 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-13 in the reply filed on 07/16/26 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou(USPGPUB DOCUMENT: 2020/0373420, hereinafter Chou) in view of Tang (USPGPUB DOCUMENT: 2023/0230930, hereinafter Tang). Re claim 1 Chou discloses a semiconductor structure, comprising: a substrate(110); a channel layer(112), disposed on the substrate(110); a barrier layer(113), disposed on the channel layer(112); a source electrode(131/141), a gate electrode(121), a drain electrode(131/141), respectively disposed on the barrier layer(113); Chou does not discloses a cap layer, wherein the conductive cap layer covers the source electrode(131/141) and the drain electrode(131/141) except the regions directly above the source electrode(131/141) and the drain electrode(131/141). Tang discloses a cap layer(105)[0020,0021], wherein the conductive cap layer(since 105 comprises AlN this may be interpreted as conductive cap) covers the source electrode(S/D) and the drain electrode(S/D) except the regions directly above the source electrode(regions covered by left/right 106) and the drain electrode(regions covered by left/right 106). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Tang to the teachings of Chou in order to improve die yield [0002, Tang]. Re claim 2 Chou and Tang disclose the semiconductor structure of claim 1, wherein the materials of the source electrode(131/141) and the drain electrode(131/141) are selected from a group consisting of titanium, aluminum, nickel, gold and a combination thereof. Re claim 4 Chou and Tang disclose the semiconductor structure of claim 1, further comprising a first metal layer, disposed above the source electrode(131/141) and the drain electrode(131/141), and electrically connected to the source electrode(131/141) and the drain electrode(131/141). Re claim 5 Chou and Tang disclose the semiconductor structure of claim 4, further comprising a liner layer(108)[0021], covering a portion of the barrier layer(113), the cap layer(105)[0020,0021], the first metal layer, and the gate electrode(121) except the other portion above the first metal layer. Re claim 6 Chou and Tang disclose the semiconductor structure of claim 5, wherein the material of the liner layer(108)[0021] is selected from a group consisting of silicon nitride, silicon dioxide, aluminum nitride, silicon carbide and a combination thereof. Re claim 7 Chou and Tang disclose the semiconductor structure of claim 4, further comprising a via structure and a second metal layer, respectively disposed above the first metal layer, and electrically connected to the first metal layer. Re claim 8 Chou and Tang disclose the semiconductor structure of claim 1, further comprising a two-dimensional electron gas, disposed at an interface between the channel layer(112) and the barrier layer(113). Re claim 9 Chou and Tang disclose the semiconductor structure of claim 1, wherein the material of the barrier layer(113) comprises AlxInyGa(1-x-y)N, where 0≦x<1,0≦x+y≦1. Re claim 10 Chou and Tang disclose the semiconductor structure of claim 1, wherein the material of the substrate(110) is selected from a group consisting of silicon, sapphire, silicon carbide and a combination thereof. Re claim 11 Chou discloses a semiconductor structure, comprising: a substrate(110); a channel layer(112), disposed on the substrate(110); a barrier layer(113), disposed on the channel layer(112); a source electrode(131/141), a gate electrode(121), a drain electrode(131/141), respectively disposed on the barrier layer(113); Chou does not discloses and a conductive cap layer, wherein the conductive cap layer covers the source electrode(131/141) and the drain electrode(131/141). Tang discloses a conductive cap layer(105)[0020,0021], wherein the conductive cap layer(since 105 comprises AlN this may be interpreted as conductive cap) covers the source electrode(S/D) and the drain electrode(S/D). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Tang to the teachings of Chou in order to improve die yield [0002, Tang]. Re claim 12 Chou and Tang disclose the semiconductor structure of claim 11, wherein the material of the conductive cap layer(105)[0020,0021] is selected from a group consisting of titanium nitride, tungsten nitride, titanium tungsten nitride, aluminum nitride, and carbon and a combination thereof. Re claim 13 Chou and Tang disclose the semiconductor structure of claim 11, further comprising a first metal layer, disposed on the conductive cap layer(105)[0020,0021] above the source electrode(131/141) and the drain electrode(131/141), and electrically connected to the conductive cap layer, the source electrode(131/141), and the drain electrode(131/141). Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou(USPGPUB DOCUMENT: 2020/0373420, hereinafter Chou) in view of Tang (USPGPUB DOCUMENT: 2023/0230930, hereinafter Tang) and Nanjo (USPGPUB DOCUMENT: 2022/0199821, hereinafter Nanjo). Re claim 3 Chou and Tang disclose the semiconductor structure of claim 1, Chou and Tang do not disclose wherein the material of the cap layer(105)[0020,0021] is selected from a group consisting of silicon nitride, silicon dioxide, silicon oxynitride and a combination thereof. Nanjo disclose wherein the material of the cap layer is selected from a group consisting of silicon nitride, silicon dioxide, silicon oxynitride and a combination thereof[claim 15]. It would have been obvious to one of ordinary skill in the art at the time of the inventions to use the material of Nanjo to replace the material of Chou’s device because such material replacement is art recognized suitability for an intended purpose. See MPEP 2144.07. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Apr 04, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.0%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 722 resolved cases by this examiner. Grant probability derived from career allowance rate.

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