DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/04/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 4-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2022/0392881 to Yu et al (hereinafter Yu).
Regarding Claim 1, Yu discloses a semiconductor package comprising:
a redistribution structure (302);
an interconnection structure (50) on the redistribution structure;
a memory stacking (326) structure disposed on the redistribution structure, and including a buffer die (250) and core dies [0078] stacked on the buffer die;
a semiconductor die (324) disposed on the buffer die and on the interconnection structure (for purposes of examination, Examiner is considering the processing die 324 as being closer to the photonic package 100 than the memory die 326; [0078]); and
an optical engine (100, Fig. 12) disposed on the interconnection structure.
Regarding Claim 2, Yu discloses the semiconductor package of Claim 1, wherein an upper surface of the buffer die and an upper surface of the interconnect structure are at the same level (Fig. 24).
Regarding Claim 4, Yu discloses the semiconductor package of Claim 1, wherein:
the interconnection structure includes a plurality of first through silicon vias connecting the semiconductor die to the redistribution structure, and the buffer die includes a plurality of second through silicon vias connecting the semiconductor die to the redistribution structure (Fig. 24).
Regarding Claim 5, Yu discloses the semiconductor package of Claim 1, wherein the interconnection structure electrically connects the semiconductor die to the optical engine (Fig. 24).
Regarding Claim 6, Yu discloses the semiconductor package of Claim 1, wherein: the semiconductor die includes a plurality of first connection members, some of the plurality of first connection members are directly connected to the buffer die, and others of the plurality of first connection members are directly connected to the interconnection structure (Fig. 24).
Regarding Claim 7, Yu discloses the semiconductor package of Claim 6, wherein the plurality of first connection members are micro bumps (Fig. 24).
Regarding Claim 8, Yu discloses the semiconductor package of Claim 1, wherein the interconnection structure is a silicon interposer [0018].
Regarding Claim 9, Yu discloses the semiconductor package of Claim 1, wherein the interconnection structure is a bridge die (Fig. 24).
Regarding Claim 10, Yu discloses the semiconductor package of Claim 9, wherein the bridge die is a silicon bridge (Fig. 24).
Regarding Claim 11, Yu discloses the semiconductor package of Claim 9, further comprising: a plurality of first conductive posts disposed between the bridge die and the buffer die and electrically connecting the semiconductor die to the redistribution structure (Fig. 24).
Regarding Claim 12, Yu discloses the semiconductor package of Claim 11, further comprising: a plurality of second conductive posts below the optical engine and electrically connecting the optical engine to the redistribution structure (Fig. 24).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu.
Regarding Claim 3, Yu discloses the semiconductor package of Claim 1 but does not explicitly disclose wherein an upper surface of the memory stacking structure, an upper surface of the semiconductor die, and an upper surface of the optical engine are at the same level.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the elements of the package such that an upper surface of the elements are at a same level to provide for a planar surface for the overall package. Figures 27 & 28 show that the elements can be at varying heights and it would have been a simple design choice for them to have the same height absent unexpected results by Applicant.
Regarding Claim 13, Yu discloses a semiconductor package comprising:
a redistribution structure (302, Fig. 24);
an interconnection structure (50) on the redistribution structure;
a memory stacking structure (326) disposed on the redistribution structure and including a buffer die (250) and core dies [0078] stacked on the buffer die;
a first molding material (208) disposed on the redistribution structure and covering the interconnection structure and the buffer die;
a semiconductor die (324) disposed on the buffer die and on the interconnection structure (for purposes of examination, Examiner is considering the processing die 324 as being closer to the photonic package 100 than the memory die 326; [0078]);
an optical engine (100) disposed on the interconnection structure; and
a second molding material disposed on the first molding material and covering the stacked core dies, the semiconductor die, and the optical engine since it would have been obvious to have used a second molding material, or encapsulation, on the final package structure of Fig. 24 to enclose the package and protect it from environmental elements.
Regarding Claim 14, Yu makes obvious the semiconductor package of Claim 13, wherein the semiconductor die includes an XPU [0086].
Regarding Claim 15, Yu makes obvious the semiconductor package of Claim 13, wherein the optical engine includes a photonic integrated circuit (PIC) and an electronic integrated circuit (EIC) on the photonic integrated circuit (PIC).
Regarding Claim 16, Yu makes obvious the semiconductor package of Claim 15, wherein the photonic integrated circuit (PIC) includes at least one of an optical waveguide, an optical modulator, a photo detector (PD), a grating coupler, and a laser diode [0029].
Regarding Claim 17, Yu makes obvious the semiconductor package of Claim 15, wherein: the photonic integrated circuit (PIC) includes a plurality of through silicon vias, and the plurality of through silicon vias electrically connect the electronic integrated circuit (EIC) to the interconnection structure [0030].
Regarding Claim 18, Yu makes obvious the semiconductor package of Claim 15, wherein: the optical engine further includes a connector, and the connector is connected to an external optical fiber (150).
Regarding Claim 19, Yu discloses a manufacturing method of a semiconductor package, comprising:
attaching a buffer die and an interconnection structure onto a carrier (Fig. 20);
molding the buffer die and the interconnection structure on the carrier with a first molding material (208);
forming core dies [0078] stacked on the buffer die (fig. 24),
mounting a semiconductor die on the buffer die and the interconnection structure (Fig. 24), and
mounting an optical engine on the interconnection structure; molding the stacked core dies (Fig. 24), the semiconductor die, and the optical engine on the first molding material with a second molding material since it would have been obvious to have used a second molding material, or encapsulation, on the final package structure of Fig. 24 to enclose the package and protect it from environmental elements;
removing the carrier to expose the buffer die and the interconnect structure (Fig. 23); and
forming a redistribution structure (302) on the buffer die and the interconnect structure (Fig. 24).
Regarding Claim 20, Yu makes obvious the manufacturing method of the semiconductor package of claim 19, further comprising: after the molding of the stacked core dies, the semiconductor die, and the optical engine on the first molding material with the second molding material, performing a chemical mechanical polishing (CMP) process on the second molding material since it would have been obvious to provide a planarized surface for the package to allow for stacking or additional manufacturing to occur over the package such as heat sink attaching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
Prosecution Insights