Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 12, and are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US20190057949A1, hereinafter Hwang).
Regarding claim 1, Hwang discloses a semiconductor device comprising:
a redistribution layer comprising an insulation layer in which a first wiring pattern is formed (Fig. 1 the redistribution layer comprising first/second/third/fourth redistribution lines 112/122/132/142 are disposed within first/second/third/fourth/fifth insulating layers 110/120/130/140/150);
a first semiconductor chip, on the redistribution layer in a first direction, connected to the first wiring pattern (Fig. 1 semiconductor chip 200 disposed on second insulating layer 120 and is connected to first redistribution layer 112); and
a first capacitor disposed in the redistribution layer (Fig. 1 capacitor 500 disposed within the redistribution layer comprising first/second/third/fourth redistribution lines 112/122/132/142 and first/second/third/fourth/fifth insulating layers 110/120/130/140/150).
Regarding claim 4, Hwang discloses
the semiconductor device of claim 1, wherein the first capacitor is disposed to be closer to a top surface of the redistribution layer facing the first semiconductor chip than a bottom surface of the redistribution layer facing away from the first semiconductor chip in the first direction (Fig. 1 would reasonably disclose and suggest to a person of ordinary skill in the art that capacitor 500 is disposed to be closer to the top surface of the redistribution layer comprising first/second/third/fourth redistribution lines 112/122/132/142 and first/second/third/fourth/fifth insulating layers 110/120/130/140/150 than the bottom surface, see MPEP 2125.I).
Regarding claim 5, Hwang discloses the semiconductor device of claim 1,
wherein the first capacitor is connected to the first wiring pattern which is connected to the first semiconductor chip (Fig. 1 capacitor 500 is connected to first redistribution line 112 which is connected to semiconductor chip 500).
Regarding claim 12, Hwang discloses an electronic device comprising:
a semiconductor chip (Fig. 16 semiconductor chip 720);
an insulation layer disposed on the semiconductor chip in a first direction (Fig. 16 first/second/third/fourth/fifth insulating layers 110/120/130/140/150, mold substrate 300, package substrate 710, and molding member 750 disposed on semiconductor chip 720), and comprising
a first wiring pattern therein which is connected to the semiconductor chip (Fig. 16 backside redistribution lines 400 electrically connected to semiconductor chip 720);
a capacitor disposed in the insulation layer (Fig. 16 capacitor 500 disposed within mold substrate 300).
Regarding claim 13, Hwang discloses the electronic device of claim 12,
wherein the capacitor is disposed in the insulation layer to be closer to a top surface of the insulation layer facing the semiconductor chip than a bottom surface of the insulation layer facing away from the semiconductor chip in the first direction (Fig. 16 would reasonably disclose and suggest to a person of ordinary skill in the art that capacitor 500 is disposed to be closer to the top surface of the insulating layers comprising first/second/third/fourth/fifth insulating layers 110/120/130/140/150, mold substrate 300, package substrate 710, and molding member 750 than the bottom surface as only package substrate 710 lies between capacitor 500 and semiconductor chip 720, see MPEP 2125.I).
Regarding claim 14, Hwang discloses the electronic device of claim 12,
wherein the insulation layer comprises a plurality of layers which are stacked in the first direction (Fig. 16 first/second/third/fourth/fifth insulating layers 110/120/130/140/150, mold substrate 300, package substrate 710, and molding member 750 are stacked in a first direction), and
wherein a thickness of the capacitor is smaller than a thickness of one of the plurality of layers in the first direction (Fig. 16 would reasonably disclose and suggest to a person of ordinary skill in the art capacitor 500 having a thickness less than molding member 750, see MPEP 2125.I).
Regarding claim 15, Hwang discloses the electronic device of claim 12,
wherein the insulation layer comprises a second wiring pattern (Fig. 16 second redistribution line 122),
wherein the capacitor is connected to the semiconductor chip though one of the first wiring pattern and the second wiring pattern (Fig. 1 semiconductor chip 720 electrically connected to capacitor 500 through backside redistribution line 400).
Regarding claim 16, Hwang discloses the electronic device of claim 12, further comprising
a connection terminal formed between the insulation layer and the semiconductor chip (Fig. 16 connection member 450 disposed between mold substrate 300 and package substrate 710),
wherein the connection terminal comprises a solder ball or a bump connecting the first wiring pattern to the semiconductor chip (Par. 88 teaches that “[t]he conductive connection members 450 may each include a solder ball or a conductive bump”).
Regarding claim 17, Hwang discloses an electronic system comprising a first semiconductor package on a substrate, the first semiconductor package comprising:
a first redistribution layer comprising a first insulation layer in which a first wiring patterns is formed (Fig. 1 the redistribution layer comprising first/second/third/fourth redistribution lines 112/122/132/142 are disposed within first/second/third/fourth/fifth insulating layers 110/120/130/140/150);
a semiconductor chip which is provided on the first redistribution layer, and connected to the first wiring pattern (Fig. 1 semiconductor chip 200 disposed on second insulating layer 120 and is connected to first redistribution layer 112); and
a first capacitor disposed in the first redistribution layer (Fig. 1 capacitor 500 disposed within the redistribution layer comprising first/second/third/fourth redistribution lines 112/122/132/142 and first/second/third/fourth/fifth insulating layers 110/120/130/140/150).
Claims 1 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US20190131273A1, hereinafter Chen).
Regarding claim 1, Chen discloses a semiconductor device comprising:
a redistribution layer comprising an insulation layer in which a first wiring pattern is formed (Fig. 3 first redistribution structure RDL1 comprises a polymer layer 102 and plurality of redistribution layers 104);
a first semiconductor chip, on the redistribution layer in a first direction, connected to the first wiring pattern (Fig. 3 semiconductor chip 300 disposed on first redistribution structure RDL1 in a first direction and is electrically connected to redistribution layers 104); and
a first capacitor disposed in the redistribution layer (Fig. 3, par. 34 teaches that “the first and second semiconductor chips 100 and 200 are decoupling capacitors” and so chip 100 is a first capacitor).
Regarding claim 8, Chen discloses the semiconductor device of claim 1, further comprising:
a second semiconductor chip, on the redistribution layer in a first direction, connected to a second wiring pattern in the redistribution layer (Fig. 3 semiconductor chip 400 disposed on first redistribution structure RDL1 in a first direction and is electrically connected to redistribution layers 108); and
a second capacitor disposed in the redistribution layer (Fig. 3, par. 34 teaches that “the first and second semiconductor chips 100 and 200 are decoupling capacitors” and so chip 200 is a second capacitor).
Regarding claim 9, Chen discloses the semiconductor device of claim 8,
wherein the first capacitor and the second capacitor are connected to the first wiring pattern and the second wiring pattern, respectively (Fig. 3 redistribution layers 104 and 108 are electrically connected to semiconductor chips 100/200), and
wherein at least one of the first wiring pattern and the second wiring pattern is connected to at least one of the first semiconductor chip and the second semiconductor chip (Fig. 3 redistribution layer is electrically connected to semiconductor chip 400).
Regarding claim 10, Chen discloses the semiconductor device of claim 8,
wherein the first capacitor and the second capacitor are disposed closer to a top surface of the redistribution layer facing the first semiconductor chip and the second semiconductor chip than an opposite outer surface of the redistribution layer facing away from the first semiconductor chip and the second semiconductor chip (Fig. 3 would reasonably disclose and suggest to a person of ordinary skill in the art RDL2 being thinner than RDL1, see MPEP 2125.I. As the semiconductor chips 100/200 are disposed between the redistribution layers RDL1/RDL2 and RDL2 is thinner, then the semiconductor chips 100/200 are disposed closer to a top surface of the redistribution layer facing the first semiconductor chip and the second semiconductor chip than an opposite outer surface of the redistribution layer facing away from the first semiconductor chip and the second semiconductor chip).
Regarding claim 11, Chen discloses the semiconductor device of claim 1, further comprising
a connection terminal between the redistribution layer and the first semiconductor chip (Fig. 3 bumps 300e),
wherein the connection terminal comprises a solder ball or a bump connecting the first wiring pattern or another wiring pattern in the redistribution layer to the first semiconductor chip (Par. 25 teaches that “the bumps 300 e may include solder bumps”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US20190057949A1, hereinafter Hwang).
Regarding claim 2, Hwang teaches the semiconductor device of claim 1,
wherein the first capacitor is disposed in the insulation layer such that one of a top surface and a bottom surface of the first capacitor is within the insulation layer in the first direction (Fig. 2 the top surface of first electrode 514 of capacitor 500 is within second insulating layer 120 in the first direction), and the other of the top surface and the bottom surface of the first capacitor is within the insulation layer in the first direction or coplanar with a top surface or a bottom surface of the insulation layer (While the bottom surface of second electrode 530 of capacitor 500 extends past the bottom surface of second insulating layer 120 and into third insulating layer 130, the primary function of capacitor 500 is to “provide various functions, such as decoupling, filtering, and/or resonance damping” [Hwang par. 36]. A rearrangement of a second electrode 530 to be coplanar with the bottom surface of second insulating layer 120 would not provide any new or unexpected results as the primary function of providing a decoupling capacitor is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange second electrode 530 to be coplanar with the bottom surface of second insulating layer 120, see MPEP 2144.04(VI)(B)).
Regarding claim 3, Hwang teaches the semiconductor device of claim 2,
wherein the top surface of the first capacitor is coplanar with the top surface of the insulation layer (Fig. 2 top surface of first electrode 514 is coplanar with top surface of second insulating layer 120).
Regarding claim 18, Hwang teaches The electronic system of claim 17,
wherein the first capacitor is disposed in the first insulation layer such that one of a top surface and a bottom surface of the first capacitor is within the first insulation layer in a first direction (Fig. 2 the top surface of first electrode 514 of capacitor 500 is within second insulating layer 120 in the first direction), and the other of the top surface and the bottom surface of the first capacitor is within the first at least one insulation layer in the first direction or coplanar with a top surface or a bottom surface of the first insulation layer (While the bottom surface of second electrode 530 of capacitor 500 extends past the bottom surface of second insulating layer 120 and into third insulating layer 130, the primary function of capacitor 500 is to “provide various functions, such as decoupling, filtering, and/or resonance damping” [Hwang par. 36]. A rearrangement of a second electrode 530 to be coplanar with the bottom surface of second insulating layer 120 would not provide any new or unexpected results as the primary function of providing a decoupling capacitor is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore rearrange second electrode 530 to be coplanar with the bottom surface of second insulating layer 120, see MPEP 2144.04(VI)(B)).
Regarding claim 19, Hwang teaches the electronic system of claim 18,
wherein the first capacitor is disposed to be closer to a top surface of the first redistribution layer facing the semiconductor chip than a bottom surface of the first redistribution layer facing away from the semiconductor chip in the first direction (Fig. 1 would reasonably disclose and suggest to a person of ordinary skill in the art that capacitor 500 is disposed to be closer to the top surface of the redistribution layer comprising redistribution lines 112/122/132/142 and insulating layers 110/120/130/140/150 than the bottom surface, see MPEP 2125.I).
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the closest prior art (US20190057949A1, US20190131273A1, US20170207147A1) teaches the semiconductor device of claim 5, wherein
a second capacitor connected to a second wiring pattern formed in the redistribution layer (Chen fig. 3 semiconductor chip 200 and par. 34 teaches that “the first and second semiconductor chips 100 and 200 are decoupling capacitors”).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the second wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip.
Examiner notes that while there are embodiments within the prior art, see Chen fig. 3, that teach a plurality of decoupling capacitor 100/200 electrically connected to wiring patterns that are electrically connected to semiconductor chips 300/400, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that the second wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip in addition with the other limitations of the independent claim.
Regarding claim 7, the closest prior art (US20190057949A1, US20190131273A1, US20170207147A1) teaches the semiconductor device of claim 1,
wherein the first capacitor is connected to the first wiring pattern (Fig. 1 capacitor 500 is connected to first redistribution line 112 which is connected to semiconductor chip 500).
However, the closest prior art does not teach in combination with the other claimed elements
wherein the first wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip.
Examiner notes that while there are embodiments within the prior art, see Wang par. 37, that teach isolating the decoupling capacitor from a base material, the cited prior art does not show an embodiment nor any motivation to combine embodiments such that the first wiring pattern is electrically isolated from any wiring pattern connected to the first semiconductor chip in addition with the other limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights