DETAILED ACTION
The Amendment filed December 29, 2025 has been entered. Claims 1-19 are pending. Claims 1 and 11 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 29, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Independent claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over independent claims 1-20 of US Patent No. 11,967,366. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant Application
US Patent 11,967,366
Comment
Claim 11. A memory, comprising:
a compute array comprising rows and columns of memory cells, the rows comprising a first pair of rows of memory cells, the first pair comprising a first row of memory cells and a second row of memory cells;
a plurality of logic gates embedded in the first pair of rows of memory cells, each comprising a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output, wherein respective logic gates of the plurality of logic gates are embedded in the first pair of rows between successive memory cells along the first and second rows, wherein at least one logic gate of the plurality of logic gates is configured to function as a first type of compute element to apply a first logic function to data values of respective memory cells of the first pair of rows of memory cells;
selection logic coupled to the plurality of logic gates, wherein the selection logic includes a two dimensional (2D) memory array to generate select lines associated with the first pair of rows of memory cells; and
sense amplifiers to drive the select lines to cause an activation of the plurality of logic gates to control compute operations including one or more of addition or multiply operations of the compute array.
Claim 1. A memory, comprising:
an array comprising rows and columns of memory cells, the rows comprising a first pair of rows of memory cells, the first pair comprising a first row of memory cells and a second row of memory cells;
a plurality of logic gates embedded in the first pair of rows of memory cells, each comprising a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output, wherein respective logic gates of the plurality of logic gates are embedded in the first pair of rows between successive memory cells along the first and second rows; and
a plurality of sense lines in the array, wherein the output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.
Note footnote1
Allowable Subject Matter
Claims 1-19 are rejected but would be allowable if overcoming nonstatutory double patenting as indicated above rejection.
Response to Arguments
Applicant’s amendment filed 12/19/2025, with respect to the rejection(s) of claims 1-19 under 35 USC 102 and 103, have been fully considered.
Regarding art rejections of the claims, the applicant’s argument with amendment of clams is persuasive. Accordingly, the examiner withdraws the art rejections.
Regarding double patenting rejection, the applicant’s argument is not persuasive. The applicant argues that the claims of US Patent No. 11,967,366 do not include compute operations. Claim 18 of the patent for this device discloses a method for performing a computation, and although the claims at issue are not completely identical, they are no substantial differences between them that would distinguish them under the patent law.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
1 Re independent claims 1 and 11, claims of US Patent recites all the claimed limitations. The various dependent claims are anticipated by/obvious in view of the conflicting patent.