DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species G, claims 1-7 and 10-20, in the reply filed on June 15, 2026 is acknowledged. Therefore, claims 1-7 and 10-20 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over by Chen et al. (US 2023/0005860, hereinafter Chen).
Regarding claim 1, Chen discloses for an integrated circuit comprising that
a cell array (memory cell array 102, Fig. 11A) disposed on a substrate (semiconductor layer 1004, Fig. 11A) and including a plurality of bit cells (a plurality of bit line drivers 306, Fig. 3), because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of bit line drivers (or column decoder), rather than a single bit line driver, because a memory array includes a plurality of bit lines and each bit line is driven by corresponding bit line driver circuitry to properly function;
a row decoder (row decoder/word line driver 308, Fig. 3, [0102]) including a plurality of word line drivers (word line drivers 308, Fig. 3, [0102]), each word liner driver configured to provide a word line signal to the cell array, because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of word line drivers (or row decoder), rather than a single word line driver, since a memory array includes a plurality of word lines and each word line is driven by corresponding word line driver circuitry to properly function, and “For example, row decoder/word line driver 308 may drive memory cells 206 coupled to the selected word line 218 using a word line voltage generated from voltage generator 310” (emphasis added, [0104]), therefore, the word line voltage in Chen corresponds to the word line signal in the claimed invention. Also, Chen further discloses that “For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an I/O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portions (e.g., a sub-circuit) of the functional circuits mentioned above, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors)” (emphasis added, [0083]), therefore, the third and fourth peripheral circuits 1116 and 1118 by Chen (Fig. 11A) can include the row decoder and word line drivers;
a backside wiring layer (interconnect layer 1126, Fig. 11A) disposed on a back side of the substrate (top-side of substrate 1004, i.e., upside-down orientation of Fig. 11A) at least partially under the row decoder (under third/fourth peripheral circuits 1116/1118, Fig. 11A); and
a plurality of backside contacts (contacts black-colored, Fig. 11A) between the row decoder (1116/1118, Fig. 11A) and the backside wiring layer (1126, Fig. 11A),
wherein each of the plurality of backside contacts (contacts black-colored, Fig. 11A) extends from a source (source of transistor 1120/1122, Fig. 11A) of at least one transistor (1120/1122, Fig. 11A) included in the plurality of word line drivers (1116/1118, Fig. 11A) to the backside wiring layer (to 1126, Fig. 11A).
Chen does not explicitly disclose that a backside wiring layer is configured to provide power to the plurality of word line drivers.
However, Chen further discloses that “HV circuit 406 may include word line driving circuits (e.g., in row decider/word line driver 308) that are coupled to word lines and apply a program voltage (Vprog) or a pass voltage (Vpass) in the range of, for example, 5V and 30V, to the word lines during program operation” ([0111]) and “the voltages provided by voltage generator 310, for example, to row decoder/word line driver 308, column decoder/bit line driver 306, and page buffer 304 are above certain levels that are sufficient to perform the memory operations” ([0108]). In view of Chen, one of ordinary skill in the semiconductor memory art would have understood that the power supply drives the word lines by supplying the required operating voltages thereto through the interconnect or wiring structure. Therefore, the interconnect layer that electrically couple the power supply to the word lines serves to provide the operating voltages used to activate the selected word lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the interconnect layer by Chen can be configured to provide the operating voltages required by the plurality of word line drivers for driving word lines, since routing power and drive voltages through the wiring layers between row decoder and the word line circuitry represents the conventional operation of semiconductor memory devices.
Regarding claim 2, Chen further discloses that a frontside wiring layer (interconnect layer 1112, Fig. 11A) disposed above a front side of the substrate (bottom side of the semiconductor layer 1004, i.e., upside-down orientation, Fig. 11A) in a vertical direction (Y direction, Fig. 11A) and including a plurality of frontside wiring patterns (contacts, black colored, Fig. 11A) configured to receive word line signals (word line voltage, [0104]) from the plurality of word line drivers (1116/1118, Fig. 11A).
Regarding claim 10, Chen further discloses for an integrated circuit, comprising that
a cell array (memory cell array 102, Fig. 11A) disposed on a substrate (semiconductor layer 1004, Fig. 11A) and including a plurality of bit cells (a plurality of bit line drivers 306, Fig. 3), because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of bit line drivers (or column decoder), rather than a single bit line driver, because a memory array includes a plurality of bit lines and each bit line is driven by corresponding bit line driver circuitry to properly function;
a plurality of word line drivers (word line drivers 308, Fig. 3, [0102]), each word line driver providing a word line signal to the cell array, because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of word line drivers (or row decoder), rather than a single word line driver, since a memory array includes a plurality of word lines and each word line is driven by corresponding word line driver circuitry to properly function, and “For example, row decoder/word line driver 308 may drive memory cells 206 coupled to the selected word line 218 using a word line voltage generated from voltage generator 310” (emphasis added, [0104]), therefore, the word line voltage in Chen corresponds to the word line signal in the claimed invention. Also, Chen further discloses that “For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an I/O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portions (e.g., a sub-circuit) of the functional circuits mentioned above, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors)” (emphasis added, [0083]), therefore, the third and fourth peripheral circuits 1116 and 1118 by Chen (Fig. 11A) can include the row decoder and word line drivers;
a frontside wiring layer (interconnect layer 1112, Fig. 11A) disposed above a front side of the substrate (bottom side of semiconductor layer 1004, i.e., upside-down orientation, Fig. 11A) in a vertical direction (Y direction, Fig. 11A) and including a plurality of frontside wiring patterns (a plurality of contacts, black-colored, Fig. 11A) configured to receive word line signals (word line voltage, [0104]) from the plurality of word line drivers (1116/1118, Fig. 11A); and
a backside wiring layer (interconnect layer 1126, Fig. 11A) disposed on a back side of the substrate (top side of semiconductor layer 1004, i.e., upside-down orientation, Fig. 11A) at least partially under the plurality of word line drivers (under 1116/1118, i.e., upside-down orientation, Fig. 11A),
wherein each of the plurality of word line drivers (1116/1118, Fig. 11A) comprises a plurality of transistors (transistors 1120/1122, Fig. 11A), and wherein each of the plurality of transistors (1120/1122, Fig. 11A) comprises a source (source of 1120/1122, Fig. 11A) connected to the backside wiring layer (1126, Fig. 11A).
Chen does not explicitly disclose that a backside wiring layer is configured to provide power to the plurality of word line drivers.
However, Chen further discloses that “HV circuit 406 may include word line driving circuits (e.g., in row decider/word line driver 308) that are coupled to word lines and apply a program voltage (Vprog) or a pass voltage (Vpass) in the range of, for example, 5V and 30V, to the word lines during program operation” ([0111]) and “the voltages provided by voltage generator 310, for example, to row decoder/word line driver 308, column decoder/bit line driver 306, and page buffer 304 are above certain levels that are sufficient to perform the memory operations” ([0108]). In view of Chen, one of ordinary skill in the semiconductor memory art would have understood that the power supply drives the word lines by supplying the required operating voltages thereto through the interconnect or wiring structure. Therefore, the interconnect layer that electrically couple the power supply to the word lines serves to provide the operating voltages used to activate the selected word lines.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the interconnect layer by Chen can be configured to provide the operating voltages required by the plurality of word line drivers for driving word lines, since routing power and drive voltages through the wiring layers between row decoder and the word line circuitry represents the conventional operation of semiconductor memory devices.
Regarding claim 11, Chen further discloses that a plurality of backside contacts (contacts, black-colored, Fig. 11A) between the plurality of word line drivers (1116/1118, Fig. 11A) and the backside wiring layer (1126, Fig. 11A), wherein the plurality of backside contacts (contacts, black-colored, Fig. 11A) each extend from sources of the plurality of transistors (source of transistors 1120/1122, Fig. 11A) to the backside wiring layer (to 1126, Fig. 11A).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0005860, hereinafter Chen) in view of Lee et al. (US 2022/0037339, Foreign priority: Jul. 31, 2020 (KR); hereinafter Lee). The teachings of Chen are discussed in claims 1 and 10 above.
Regarding claim 17, Chen further discloses an integrated circuit, comprising that
a cell array (memory cell array 102, Fig. 11A) including a plurality of bit cells (a plurality of bit line drivers 306, Fig. 3), because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of bit line drivers (or column decoder), rather than a single bit line driver, because a memory array includes a plurality of bit lines and each bit line is driven by corresponding bit line driver circuitry to properly function;
a plurality of word line drivers (word line drivers 308, Fig. 3, [0102]), each word line driver providing a word line signal to the cell array, because it would have been obvious to one of ordinary skill in the semiconductor memory art that the memory device includes a plurality of word line drivers (or row decoder), rather than a single word line driver, since a memory array includes a plurality of word lines and each word line is driven by corresponding word line driver circuitry to properly function, and “For example, row decoder/word line driver 308 may drive memory cells 206 coupled to the selected word line 218 using a word line voltage generated from voltage generator 310” (emphasis added, [0104]), therefore, the word line voltage in Chen corresponds to the word line signal in the claimed invention. Also, Chen further discloses that “For example, the peripheral circuits can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an I/O circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portions (e.g., a sub-circuit) of the functional circuits mentioned above, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors)” (emphasis added, [0083]), therefore, the third and fourth peripheral circuits 1116 and 1118 by Chen (Fig. 11A) can include the row decoder and word line drivers;
a frontside wiring layer (interconnect layer 1112, Fig. 11A) disposed above the plurality of word line drivers (above 1116/1118, i.e., upside-down orientation, Fig. 11A) in a vertical direction (Y direction, Fig. 11A) and including a plurality of frontside wiring patterns (contacts, black-colored, Fig. 11A) configured to receive word line signals (word line voltage, [0104]) from the plurality of word line drivers (1116/1118, Fig. 11A);
a backside wiring layer (interconnect layer 1126, Fig. 11A) disposed under the plurality of word line drivers (under 1116/1118, i.e., upside-down orientation, Fig. 11A) in the vertical direction (Y direction, Fig. 11A) and including a first backside wiring pattern (contact pads (diagonally striped) on the left side in 1126, Fig. 11A) and a second backside wiring pattern (contact pads (diagonally striped) on the right side in 1126, Fig. 11A);
a plurality of first backside contacts (contacts (black-colored) on the left side in 1126, Fig. 11A) between the plurality of word line drivers (1116/1118, Fig. 11A) and the first backside wiring pattern (contact pads (diagonally striped) on the left side in 1126, Fig. 11A); and
a plurality of second backside contacts (contacts (black-colored) on the right side in 1126, Fig. 11A) between the plurality of word line drivers (1116/1118, Fig. 11A) and the second backside wiring pattern (contact pads (diagonally striped) on the right side in 1126, Fig. 11A).
Chen does not explicitly disclose that a first backside wiring pattern configured to provide a power supply voltage to the plurality of word line drivers and a second backside wiring pattern configured to provide a ground voltage to the plurality of word line drivers.
However, Lee discloses that the memory device including a memory cell 10 having a pair of inverters (i.e., first and second inverters INV1 and INV2) receiving the positive supply voltage VDD and the negative supply voltage (or ground voltage) VSS ([0048]), and one of ordinary skill in the semiconductor memory art would have recognized that the word line drivers require both VDD and VSS to operate and these supply voltages are conventionally distributed through separate wiring layers. Because Lee further discloses back-end-of-line (BEOL) structure (Fig. 3), it is obvious to configure a first backside wiring pattern to provide VDD and a second backside wiring pattern to provide VSS to a plurality of word line drivers as applying a known technique to a known device, in other words, a predictable implementation of disclosed by BEOL structure by Lee.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the positive and negative (or ground) supply voltages (VDD/VSS) of Lee into the interconnect layers of memory device structure disclosed by Chen, since it is well-known conventional power distribution technique to improve power delivery and routing efficiency in integrated circuits.
Allowable Subject Matter
Claims 3-7, 12-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claimed limitation, “each of the plurality of word line drivers comprises at least one P-type transistor and at least one N-type transistor” of claim 3, 12 and 18, and claims 4-7 depend on claim 3, claims 13-16 depend on claim 12, and claims 19-20 depend on claim 18.
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights