DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 04/04/2024.
Currently claims 1-17 are pending in the application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/20/2026 and 04/04/2024 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-17 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 1, the instant claim recites “wherein the end surface is formed with a first portion, the first portion includes at least one of a projecting portion protruding from the end surface or a recessed portion recessed from the end surface, the projecting portion is located outside an outer edge of the mounting surface as viewed in the thickness direction, and the recessed portion is enclosed in the outer edge as viewed in the thickness direction" (claim 1, lines 11-18). In the first part of the limitation, it requires only one of the options, the ‘projecting portion’ or the ‘recessed portion’. However, in the last part, the “recessed portion” appeared as “and” which means that both the options are required. It makes the claim ambiguous, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the examiner did not give any weight to the second option (recessed portion).
Claims 2-17 are also rejected due to their dependence on a rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0388580 A1 (Furutani) and further in view of JP 2016136648 A (Nakamura).
Regarding claim 1, Furutani discloses, a semiconductor device comprising:
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a lead (1A; first lead; Figs 1 and 3; [0043]) including a mounting surface (111A; obverse surface; Fig. 3 and 6; [0044]) facing in a thickness direction and an end surface (122A; second surface; Fig. 3 and 6; [0044]) facing in a direction orthogonal to the thickness direction (z-direction) and connected to the mounting surface (111A) (as evident in Fig. 6);
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a semiconductor element (3 and 5; first and second semiconductor elements; Fig. 1; [0045]) bonded to the mounting surface (111A); and
a sealing resin (7; sealing resin; Fig. 6; [0037]) covering the semiconductor element (3 and 5) and in contact with the mounting surface (111A) and the end surface (122A),
But Furutani fails to teach explicitly, wherein the end surface is formed with a first portion, the first portion includes at least one of a projecting portion protruding from the end surface or a recessed portion recessed from the end surface, the projecting portion is located outside an outer edge of the mounting surface as viewed in the thickness direction, and the recessed portion is enclosed in the outer edge as viewed in the thickness direction.
However, in analogous art, Nakamura discloses, wherein the end surface (11; terminal part; Fig. 4a; page 4) is formed with a first portion (as annotated on Fig. 4), the first portion includes at least one of a projecting portion (M; projecting portion; Fig. 4a; page 4) protruding from the end surface (11) or a recessed portion recessed from the end surface,
the projecting portion (M) is located outside an outer edge (p1; outer peripheral edge; Fig. 4a; page 4) of the mounting surface (front surface 11a; Fig. 4a; page 4) as viewed in the thickness direction (z), and the recessed portion is enclosed in the outer edge as viewed in the thickness direction (the examiner used one of the options, i.e., projecting portion).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Furutani and Nakamura before him/her, to modify the teachings of a semiconductor lead frame as taught by Furutani and to include a protruding portion at the end portion of a lead as taught by Nakamura since protruding portion helps in suppressing the resin layer being peeled off from the lead frame (page 4). Absent this important teaching in Furutani, a person with ordinary skill in the art would be motivated to reach out to Nakamura while forming a semiconductor lead frame of Furutani.
Regarding claim 2, the combination of Furutani and Nakamura discloses, the semiconductor device according to claim 1, wherein the first portion (specifically the tip p3 of first portion) is spaced apart from the outer edge (p1) (Fig. 4a; page 4; Nakamura Ref.).
Regarding claim 12, Furutani discloses, the semiconductor device according to claim 1, further comprising a substrate (6; supporting member; Fig. 1; [0037]) including an obverse surface (top of substrate 6) facing a same side as the mounting surface (111A) in the thickness direction (z), wherein the lead (1A) includes a die pad portion (as annotated on Fig. 3) including the mounting surface (111A) and the end surface (122A) and a terminal portion (104A; as annotated on Fig. 3; [0071]) connected to the die pad portion (as annotated on Fig. 3), and the die pad portion is bonded to the obverse surface (Fig. 3; [0043] – [0044]).
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Regarding claim 13, Furutani discloses, the semiconductor device according to claim 12, wherein the semiconductor element (3) is electrically bonded (with bonding layer 39) to the mounting surface (111A) (Fig. 3; [0155]).
Regarding claim 14, Furutani discloses, the semiconductor device according to claim 12, wherein the obverse surface (61, top of substrate 6) includes a first edge (66; Fig. 3; [0170]) extending in a first direction (x) orthogonal to the thickness direction (z) and a second edge (63; Fig. 3; [0170]) extending in a direction (y) orthogonal to the thickness direction (z) and the first direction (x), and the terminal portion (104A) overlaps with the first edge (66) as viewed in the thickness direction (z).
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Regarding claim 15, Furutani discloses, the semiconductor device according to claim 14, wherein the first edge (66) is longer than the second edge (63) (as evident in Fig. 3).
Regarding claim 16, Furutani discloses, the semiconductor device according to claim 15, wherein the sealing resin (7) is formed with a plurality of attaching portions (710 and 720; recesses; Fig. 3; [0185]) extending throughout the sealing resin (7) in the thickness direction (z), and the plurality of attaching portions (710 and 720) are provided on either side of the substrate (6) in the first direction (x).
Regarding claim 17, Furutani discloses, the semiconductor device according to claim 12, wherein the substrate (6) includes a reverse surface (62; reverse surface; Fig. 3; [0170]) facing away from the obverse surface (61) in the thickness direction (z), and the reverse surface (62) is exposed from the sealing resin (7; as evident in Fig. 6).
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 3, the closest prior art, US 2020/0388580 A1 (Furutani), in conjunction with JP 2016136648 A (Nakamura), and in combination with the other claimed features, fails to disclose, “the semiconductor device according to claim 1, wherein the first portion includes a first surface and a second surface each facing a same side as the end surface in a direction orthogonal to the thickness direction, the second surface is located between the mounting surface and the first surface in the thickness direction, and the first surface and the second surface are spaced apart from the outer edge as viewed in the thickness direction”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘wherein the first portion includes a first surface and a second surface each facing a same side as the end surface in a direction orthogonal to the thickness direction, the second surface is located between the mounting surface and the first surface in the thickness direction, and the first surface and the second surface are spaced apart from the outer edge as viewed in the thickness direction,’ is material to the inventive concept of the application at hand to improve lead-resin bonding and strengthen it without greatly complicating the overall package structure.
Regarding claim 10, the closest prior art, US 2020/0388580 A1 (Furutani), in conjunction with JP 2016136648 A (Nakamura), and in combination with the other claimed features, fails to disclose, “the semiconductor device according to claim 1, wherein the end surface is formed with a second portion, and the second portion is recessed from the end surface and extends throughout the lead in the thickness direction”, in combination with the additionally claimed features, as are claimed by the Applicant.
Specifically, the aforementioned ‘the semiconductor device according to claim 1, wherein the end surface is formed with a second portion, and the second portion is recessed from the end surface and extends throughout the lead in the thickness direction,’ is material to the inventive concept of the application at hand to improve lead-resin bonding and strengthen it without greatly complicating the overall package structure.
Claims 4-9 and 11 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0077052 A1 (Ge) - A Quad Flat No-Lead (QFN) package is disclosed comprising a semiconductor die, a lead frame and molding compound. The lead frame comprises a die pad having a substantially rectangular inner part and a plurality of protrusions around the periphery thereof and contiguous therewith and extending outwardly therefrom, and a plurality of leads around the four sides of the die-pad. The molding compound encapsulates the semiconductor die and forming the package. The molding compound has a respective moat therein between each side of the die pad and a respective set of leads. The die pad has a plurality of trenches extending from the second surface of the die pad towards the first surface at least in the inner part of the die pad. The plurality of the trenches each extend across a protrusion to the moat.
US 2020/0321261 A1 (Fujino) - A semiconductor package is disclosed includeing an insulating substrate; a first semiconductor chip; a second semiconductor chip with a thickness smaller than a thickness of the first semiconductor chip; a heat radiation member in which a main surface located on an opposite side of an active surface of the first semiconductor chip and an active surface of the second semiconductor chip, respectively, are bonded to a lower surface; and a sealing resin having contact with at least part of a side wall of the heat radiation member without being raised over an upper surface of the heat radiation member to seal the first and second semiconductor chips on the insulating substrate, wherein in the heat radiation member, a thickness of a first bonding part to which the first semiconductor chip is bonded is smaller than a thickness of a second bonding part to which the second semiconductor chip is bonded.
US 2020/0075440 A1 (Majima) - A semiconductor device is disclosed including a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
06/05/2026
Prosecution Insights