DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-15 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim US 2022/0165678 A1 in view of Ma et al. US 2015/0130030 A1.
Regarding claims 1 and 7-10, Kim discloses:
A semiconductor package (i.e. refer to Fig. 1), comprising:
a substrate (110) comprising an interconnection (115);
a chip stack (130) comprising a plurality of semiconductor chips (130a-130h) stacked on the substrate;
bonding wires (150) electrically coupling the plurality of semiconductor chips to the interconnection;
a protective layer (160/162) on the chip stack and comprising a first insulating resin (para 0046; polyimide);
a mold (170) at least partially covering the chip stack and the protective layer, the mold comprising an insulating resin comprising fillers dispersed in the insulating resin (para 0055); and
connection bumps electrically coupled to the interconnection below the substrate.
Kim does not disclose:
the protective layer comprising first fillers dispersed in the first insulating resin;
the mold comprising second fillers dispersed in the second insulating resin; and
wherein a first average diameter of the first fillers is smaller than a second average diameter of the second fillers, and wherein a first concentration of the first fillers in the first insulating resin is lower than a second concentration of the second fillers in the second insulating resin.
Ma discloses a publication from a similar field of endeavor in which:
a first insulating layer (610) comprising first fillers (paras 0127 and 0111) dispersed in the first insulating resin;
a second insulating layer (620) comprising second fillers (paras 0127 and 0111) dispersed in the second insulating resin; and
wherein a first average diameter of the first fillers is smaller than a second average diameter of the second fillers (para 0127), and wherein a first concentration of the first fillers in the first insulating resin is lower than a second concentration of the second fillers in the second insulating resin (para 0111).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first and second fillers having the claimed average diameter and concentration criteria as taught by Ma within the similar protective layer and mold features of Kim to reduce potential physical damage to the chips during processing or in general usage by adjusting the Young’s modulus accordingly.
(claim 7) Kim; 160 covering 130h upper chip of the stack.
(claim 8) Kim; paras 0046 and 0055.
(claims 9 and 10) Ma; para 0127.
Regarding claims 2-4, as in the combination above, although Ma does not specifically disclose “(claim 2) wherein the first average diameter ranges from about 1 micrometer (µm) to about 10 µm, and wherein the second average diameter ranges from about 10 µm to about 30 µm; (claim 3) wherein a first maximum diameter of the first fillers is less than or equal to about 20 micrometers (µm), and wherein a second maximum diameter of the second fillers is greater than or equal to about 40 µm; and (claim 4) wherein the first concentration ranges from about 50 percent by weight (wt%) to about 70 wt%, and wherein the second concentration ranges from about 80 wt% to about 90 wt%”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed ranges of the average diameter, maximum diameter and concentration of the first and second fillers of Ma since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 5, as in the combination above, Kim discloses:
wherein the protective layer (160) comprises a first surface (top) in contact with the mold (170).
Although Kim does not specifically disclose “wherein the first surface comprises a curved surface”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that since the protective layer of Kim is formed or polyimide, as noted in para 0046, there would be a residual curvature, albeit not substantial, at least at the upper corners of 160 since the material is polymer based.
Regarding claim 11, as in the combination above, although Kim does not specifically disclose “wherein a distance between an uppermost semiconductor chip from among the plurality of semiconductor chips and an upper surface of the mold is less than or equal to about 140 micrometers (µm)”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed distance between of the uppermost semiconductor chip 130h and upper surface of the mold 170 of Kim since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 12-15, as in the combination above, although Ma does not specifically disclose “(claim 12) wherein an indentation strength of the semiconductor package is greater than or equal to about 40 newtons (N). 13; (claim 13) wherein the indentation strength is obtained by measuring a maximum force before a crack occurs in an uppermost semiconductor chip from among the plurality of semiconductor chips with respect to a force pressing on an upper portion of the mold at least partially covering the protective layer; (claim 14) wherein a bending property of the semiconductor package is greater than or equal to about 3000 micrometer (µm); and (claim 15) wherein the bending property is obtained by measuring a maximum displacement before a crack occurs in an uppermost semiconductor chip from among the plurality of semiconductor chips with respect to a force bending the semiconductor package into a "U" shape SO that the chip stack faces outwardly”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine both the indentation strength and bending property ranges as claimed base on Ma’s discussion, in para 0127, of adjusting the Young’s Modulus or elastic coefficient between the two insulating layers 610 and 620 to reduce potential physical damage to the chips during processing or in general usage by adjusting the Young’s modulus accordingly. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 18, Kim discloses:
A semiconductor package (i.e. refer to Fig. 1), comprising:
a substrate (110) comprising an interconnection (115);
a chip stack (130) comprising a plurality of semiconductor chips (130a-130h) stacked on the substrate;
bonding wires (150) electrically coupling the plurality of semiconductor chips to the interconnection;
a protective layer (160/162) on the chip stack and comprising a first insulating resin (para 0046; polyimide);
a mold (170) at least partially covering the chip stack and the protective layer, the mold comprising fillers (para 0055)
Kim does not disclose:
a protective layer comprising first fillers;
the mold comprising second fillers; and
wherein a first concentration of the first fillers in the protective layer is lower than a second concentration of the second fillers in the mold.
Ma discloses a publication from a similar field of endeavor in which:
a first insulating layer (610) comprising first fillers (paras 0127 and 0111);
a second insulating layer (620) comprising second fillers (paras 0127 and 0111); and
wherein a first concentration of the first fillers in the first insulating resin is lower than a second concentration of the second fillers in the second insulating resin (para 0111).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first and second fillers having the claimed concentration criteria as taught by Ma within the similar protective layer and mold features of Kim to reduce potential physical damage to the chips during processing or in general usage by adjusting the Young’s modulus accordingly.
Regarding claims 19 and 20, as in the combination above, although Ma does not specifically disclose “(claim 19) wherein the first concentration is less than or equal to about 70 percent by weight (wt%); and (claim 20) wherein a maximum diameter of the first fillers is less than or equal to about 20 micrometer (µm)”, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the claimed ranges of the maximum diameter and concentration of the first and second fillers of Ma since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 6, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim US 2022/0165678 A1 in view of Ma et al. US 2015/0130030 A1 in further view of Song et al. US 2015/0102506 A1.
Regarding claim 6, Kim/Ma do not disclose:
wherein a thickness of the protective layer is reduced toward an edge of the protective layer.
Song discloses a publication from a similar field of endeavor in which:
wherein a thickness of an overlying insulating layer (450; para 0043) is reduced toward an edge of the protective layer (450 shown with thinner thickness over wire bonding pad 440) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the thickness criteria of the insulating layer of Song within the similar protective layer of Kim/Ma to reduce scaling of the overall semiconductor package particularly preferable in mobile devices.
Regarding claim 16, Kim discloses:
A semiconductor package (i.e. refer to Fig. 1), comprising:
a substrate (110) comprising an interconnection (115);
a chip stack (130) comprising a plurality of semiconductor chips (130a-130h) stacked on the substrate;
bonding wires (150) electrically coupling the plurality of semiconductor chips to the interconnection;
a protective layer (160/162) on the chip stack and comprising a first insulating resin (para 0046; polyimide);
a mold (170) at least partially covering the chip stack and the protective layer, the mold comprising fillers (para 0055)
Kim does not disclose:
a protective layer comprising first fillers;
the mold comprising second fillers; and
wherein the protective layer comprises a first portion having a first thickness and a second portion having a second thickness, the second thickness being different from the first thickness.
Ma discloses a publication from a similar field of endeavor in which:
a first insulating layer (610) comprising first fillers (paras 0127 and 0111);
a second insulating layer (620) comprising second fillers (paras 0127 and 0111); and
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first and second fillers as taught by Ma within the similar protective layer and mold features of Kim to reduce potential physical damage to the chips during processing or in general usage by adjusting the Young’s modulus accordingly.
Kim/Ma do not disclose:
wherein the protective layer comprises a first portion having a first thickness and a second portion having a second thickness, the second thickness being different from the first thickness.
Song discloses a publication from a similar field of endeavor in which:
wherein an insulating layer (450; para 0043) comprises a first portion having a first thickness and a second portion having a second thickness, the second thickness being different from the first thickness (450 shown with thinner thickness over wire bonding pad 440) (Fig. 1A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the thickness criteria of the insulating layer of Song within the similar protective layer of Kim/Ma to reduce scaling of the overall semiconductor package particularly preferable in mobile devices.
(claim 17) Song; Fig. 1A.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893
Prosecution Insights