DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 10 is objected to because of the following informalities: claim 10 recites: “the ignition-deposited metal layer” which lacks an antecedent basis. For examination purposes, “the ignition-deposited metal layer” is interpreted to be “an ignition-deposited metal layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satou et al. U.S. Patent 5,294,321 (the ‘321 reference).
Referring to claim 1, the ‘321 reference discloses a method, comprising:
providing a semiconductor structure (semiconductor device, col. 1, lines 15-20) on a substrate (such as a circuit board, not disclosed, inherent for the semiconductor structure to function);
providing a metastable reactive layer (sputtering target MSix, col. 6, lines 60-68) on the semiconductor structure; and
applying energy (heat, col. 6, line 65 to col. 7, line 5) to the metastable reactive layer (MSix) to form a silicide layer (MSi2, col. 7, lines 34-40) on the semiconductor structure.
Referring to claim 2, the reference further discloses that applying the energy to the metastable reactive layer (MSix) to form the silicide layer (MSi2) on the semiconductor structure comprises:
catalyzing an ignition (exothermic reaction, col. 7, lines 1-5) of the metastable reactive layer (MSix) with the energy; and
providing the silicide layer (MSi2) on the semiconductor structure based on the ignition.
4. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shue et al. U.S. Patent 5,744,395 (the ‘395 reference).
Referring to claim 1, the ‘395 reference discloses a method, comprising:
providing a semiconductor structure (metal oxide semiconductor field effect transistor MOSFET, Fig. 8, col. 3, lines 18-25) on a substrate (1);
providing a metastable reactive layer (metastable-phase titanium silicide 11a, Fig. 4, col. 4, lines 30-35) on the semiconductor structure (MOSFET); and
applying energy (rapid thermal anneal, col. 4, lines 45-50) to the metastable reactive layer (11a) to form a silicide layer (titanium silicide 11b) on the semiconductor structure (MOSFET).
5. Claims 14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ji et al. U.S. Patent Application Publication 2022/0139793 A1 (the ‘793 reference).
Referring to claim 14, the ‘793 reference discloses a semiconductor device package, comprising:
a submount (not depicted in Fig. 1B, para [70]; submount 1010, Fig. 10B, para [115]);
a semiconductor structure (120, para [69]; 1020, para [113]) comprising a [metastable-reactive-layer-deposited] silicide (19, para [70]); and
a metallization layer (nickel layer and/or cathode 20/18, para [70]) on the [metastable-reactive-layer-deposited] silicide (19), the metallization layer (20/18) between the submount (said not-depicted) and the semiconductor structure (120).
Note that the limitation “metastable-reactive-layer-deposited” in “metastable-reactive-layer-deposited silicide” has not been given patentable weight in this claim draw to a structure, because distinct structures (as claimed and as compared to the prior art’s) are not necessarily produced. See MPEP 2112.01 and MPEP 2113.
Referring to claims 16 and 17, in a manner similar to that detailed above for claim 14, the limitation “metastable-reactive-layer-deposited”, “are formed based on an isolated exothermic reaction between the submount and the semiconductor structure, and wherein the isolated exothermic reaction is catalyzed by energy applied to a nano-thermite structure between the submount and the semiconductor structure, the energy being one of an electrical spark, a laser pulse, or an applied voltage” and “wherein the nano-thermite structure comprises one or more metastable nano-thermites, the one or more metastable nano-thermites comprising one of aluminum-copper oxide (Al/CuOX), aluminum-platinum (Al/Pt), palladium-aluminum (Pd/Al), nickel-aluminum (Ni/Al), zirconium-aluminum-cupronickel (Zr/Al/CuNi), silylrhodium (Rh/Si), a niobium-silicide (Nb/Si), a zirconium-silicide (Zr/Si), or a titanium-silicide (Ti/Si)” have not been given patentable weight in this claim draw to a structure, because the claimed end product comprises a silicide and a metallization layer on the silicide.
Referring to claim 18, the reference further discloses a die-attach material (not depicted in Fig. 1B; die attach layer 1011, Fig. 10B, para [115]) coupling the metallization layer (20/18, Fig. 1B; not depicted in Fig. 10B) to the submount (not depicted in Fig. 1B; submount 1010 in Fig. 10B). Note that the limitation “wherein the isolated exothermic reaction fuses the die-attach material to the metallization layer” is considered to be a product-by-process limitation and has been taken to be a non-limitation in the device claim; specifically, a product-by-process limitation is only evaluated to determine the final claimed properties and claimed characteristics of the product (MPEP 2113 [R-1]); in the instant case, no claimed properties and characteristics can be found for the purpose of comparing with the prior art; and as such, said limitation has been considered to be a non-limitation.
Referring to claim 19, the reference further discloses that the metallization layer (20/18) is a backside metallization structure for the semiconductor device package, the backside metallization structure being a drain electrode (cathode 18, para [5, 70], [5]: “drain may be on the bottom surface of the semiconductor layer structure). For example, power Schottky diodes typically have a vertical structure where the anode contact is formed on a first major surface (e.g., the top surface) of a semiconductor layer structure, and the cathode contact is formed on the other major surface (e.g., the bottom surface)”, [70]: “cathode ohmic layer(s) may include one or more layers of ohmic metal, such as a nickel (Ni) layer 20 and a nickel silicide (NiSi) layer 19. While not shown, one or more additional layers may be formed on the cathode contact 18 to define a backside metal stack for attachment to a package submount”) for the semiconductor structure.
Referring to claim 20, the reference further discloses that the semiconductor structure comprises a wide bandgap semiconductor (para [2, 69]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3-4, 9 and 13 are rejected under 35 U.S.C. §103 as being unpatentable over Satou et al. U.S. Patent 5,294,321 (the ‘321 reference) in view of Nagata et al. U.S. Patent Application Publication 2023/0122519.
Referring to claims 3-4 and 9, the ‘321 reference discloses an electrode or wiring comprising the silicide layer (MSi2) as detailed above for claims 1 and 2, but does not disclose a metal layer or a metallization structure on the silicide layer.
Nagata, in disclosing a wiring structure, teaches a metallization structure comprising a metal layer 43 (Fig. 5) on a silicide layer 17 (para [88]) to suppress forming of whiskers (para [05-06] (paragraph(s) [0005]-[0006])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s wiring with a metallization structure comprising a metal layer on the silicide layer (MSi2). One would have been motivated to make such a modification in view of the teachings in Nagata to suppress forming of whiskers.
Thus, such a modification would have resulted in a method comprising or wherein:
referring to claim 3, applying the energy to the metastable reactive layer (MSix) to form the silicide layer (MSi2) on the semiconductor structure further comprises:
providing a metal layer (43, as taught by Nagata) on the silicide layer (MSi2) based on the ignition,
wherein the metal layer (43) would have comprised an aluminum alloy (TiAl, Nagata, para [88]);
referring to claim 4, providing a metallization structure (comprising metal layer 43, as taught by Nagata) on the silicide layer (MSi2);
referring to claim 9 and using the same reference characters, interpretations, and citations as detailed above for claims 1 and 2 where applicable,
providing a semiconductor structure (semiconductor device) on a substrate;
providing a thermite structure (sputtering target MSix) on the semiconductor structure;
providing an ignition-deposited silicide layer (MSi2) on the semiconductor structure; and
providing a metallization structure (comprising metal layer 43, as taught by Nagata) on the ignition-deposited silicide layer (MSi2);
and
referring to claim 13, the ignition-deposited silicide layer (MSi2) comprises a refractory metal silicide such as titanium silicide (col. 9, lines 30-40), meeting the claim limitation “one of a nickel-silicide (NiSi) layer or titanium silicide (Ti5Si3)”.
7. Claims 4-6 are rejected under 35 U.S.C. §103 as being unpatentable over Shue et al. U.S. Patent 5,744,395 (the ‘395 reference) in view of Nagata et al. U.S. Patent Application Publication 2023/0122519.
Referring to claim 4-5, the ‘395 reference discloses a contact/wiring comprising the silicide layer (11b) as detailed above for claim 1, but does not disclose a metallization structure on the silicide layer, wherein the metallization structure comprises a titanium alloy.
Nagata, in disclosing a contact/wiring structure, teaches a metallization structure comprising a metal layer 43 (Fig. 5) on a silicide layer 17 (para [88]) to suppress forming of whiskers (para [05-06] (paragraph(s) [0005]-[0006])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s wiring with a metallization structure comprising a metal layer on the silicide layer (11b). One would have been motivated to make such a modification in view of the teachings in Nagata to suppress forming of whiskers.
Thus, such a modification would have resulted in a method comprising or wherein:
referring to claim 4, providing a metallization structure (comprising metal layer 43, as taught by Nagata) on the silicide layer (11b);
referring to claim 5, providing the metallization structure on the silicide layer comprises:
removing a metal layer (10) from the silicide layer (11b) (Figs. 5-6, col. 4, lines 64-67); and
providing the metallization structure (comprising metal layer 43, as taught by Nagata) on the silicide layer, wherein the metallization structure (43) would have comprised a titanium alloy (TiAl, Nagata, para [88]);
and
referring to claim 6, the metallization structure (comprising metal layer 43, as taught by Nagata) and the silicide layer (11b; Nagata’s 17) would have formed an ohmic contact (Nagata, para [65]) for a semiconductor device.
8. Claim 7 is rejected under 35 U.S.C. §103 as being unpatentable over Satou et al. U.S. Patent 5,294,321 (the ‘321 reference) in view of Summers et al. U.S. Patent 8,847,373 B1.
Referring to claim 7, the ‘321 reference discloses the energy applied to the metastable reactive layer (MSix) as detailed above for claim 1 and further discloses that the energy catalyzes an isolated (locally) exothermic reaction (col. 7, lines 1-5) in the metastable reactive layer, but does not disclose that the energy is one of an electrical spark, a laser pulse, or an applied voltage.
Summers, in disclosing an exothermic reaction, discloses that the exothermic reaction can be initiated by application of laser light, or application of current to a current-carrying conductor, thereby teaching that a laser pulse or an applied voltage is a suitable energy to start an exothermic reaction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have utilized a laser pulse or an applied voltage as the energy. One would have been motivated to make such a modification in view of the teachings in Summers that a laser pulse of an applied voltage is a suitable energy to start an exothermic reaction.
Allowable Subject Matter
9. Claims 8, 10-12 and 15, insofar as in compliance with the claim objections detailed above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a method and a semiconductor device package with all exclusive limitations as recited in claims 8, 10 and 15, which may be characterized (claim 8) in providing a nickel layer on the semiconductor structure, providing a silicon layer on the nickel layer, and providing the metastable reactive layer on the silicon layer, (claim 10) in that an ignition-deposited metal layer is provided on the ignition-deposited silicide layer based on the ignition, and (claim 15) in that nano-thermite residue is on the semiconductor structure.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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06-09-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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