Office Action Predictor
Last updated: April 16, 2026
Application No. 18/627,179

PCB For An IC Chip With D-PHY Function And C-PHY Function And An PCB Assembly Including The IC Chip

Non-Final OA §102§112
Filed
Apr 04, 2024
Examiner
TRAN, BINH BACH THANH
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Aptiv Technologies AG
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
545 granted / 680 resolved
+12.1% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 680 resolved cases

Office Action

§102 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 – 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, lines 3 – 4 recites “D-PHY” and “C-PHY”. This renders the claim indefinite for several reasons. The Applicant has not provided the Office with any documentation of exactly what this standard is. It is further unknown what revision number (if any) the Applicant is referring to. Additionally, a recitation referencing an external standard in a claim as a limitation further renders the claim indefinite because there is no way of knowing that such a standard will be consistent in the future and remain unchanged. Therefore, the scope of the claim invention may or may not change in the future and there is simply no way of predicting the future. Furthermore, there is also no way of knowing whether policy related to the maintaining numbering conventions, rules on revision numbers and test numbers, or any other identifying marks to this procedure will remain completely unchanged in the future. Unforeseeable circumstances or changes may occur at any time to policy of this standard or identifying nomenclature, even if there is no history of such changes until the present. As such, it is unknown that the scope of the claim would remain consistent and the public may be unable to identify if and when any infringement may or may not occur. Therefore, the claim is indefinite. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 - 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Itoigawa (US 20170032757). Regarding claim 1, Itoigawa discloses a printed circuit board (PCB 3A, Fig. 7A) comprising: a first pin pad (one of the terminals 12, Fig. 7A) adapted to be connected to a first pin of an integrated circuit (IC 2), wherein the first pin of the IC chip is a pin for a D-PHY function and a C-PHY function provided by the IC chip (the lines from the IC are either D-PHY or C-PHY depend upon the switch inside the IC 2); a first wire (one of the line 11 as a D-PHY line) adapted as a line for the D-PHY function; a second wire (one of the line 11 as C-PHY) adapted as a line for the C-PHY function; and a first assembly option module (A1) adapted to provide a first option of connecting the first pin pad to the first wire if the IC chip to be assembled onto the PCB is to provide the D-PHY function (when the switch inside IC turn on D-PHY, then the line will be the D-PHY line), or to provide a second option of connecting the first pin pad to the second wire if the IC chip to be assembled onto the PCB is to provide the C-PHY function. Regarding claim 2, Itoigawa discloses the claimed invention as set forth in claim 1. Itoigawa further suggests the first assembly option module is adapted to provide a third option of connecting the second wire to ground (the assembly, in Fig. 6, provide a path to ground when the switch to ground is on) if the IC chip to be assembled onto the PCB is to provide the D-PHY function. Allowable Subject Matter Claims 3 – 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the first wire is a first line for a Clock Lane of the D-PHY function, and the second wire is a first line for a first trio of the C-PHY function. None of the reference art of record discloses or renders obvious such a combination. Regarding claim 7, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that each of the first assembly option module and the second assembly module comprises: a first assembly option pad connected to the first wire or the sixth wire, a second assembly option pad connected to the second wire or the seventh wire, and a third assembly option pad connected to the first pin pad or the fourth pin pad, wherein the first assembly option pad, the second assembly option pad, and the third assembly option pad are not electrically connected with each other, and are so arranged that, as the first option, the first assembly option pad and the third assembly option pad can be electrically connected through a first conductor or a fourth conductor, and, as the second option, the second assembly option pad and the third assembly option pad can be electrically connected through a second conductor or a fifth conductor. None of the reference art of record discloses or renders obvious such a combination. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hori (US 20230058759) discloses D-PHY and C-PHY switch, Fig. 2B & 2C. Lee (US 20220060358) discloses D-PHY and C-PHY circuitry, Fig. 1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH B TRAN/Primary Examiner, Art Unit 2848
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Prosecution Timeline

Apr 04, 2024
Application Filed
Jan 16, 2026
Non-Final Rejection — §102, §112
Mar 29, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
99%
With Interview (+22.1%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 680 resolved cases by this examiner. Grant probability derived from career allow rate.

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