Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 & 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 8, 21 - 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boja (US 20240222213).
Regarding claim 1, Boja discloses a printed circuit board, comprising:
a first insulating layer (the monolithic core 102a, Fig. 4) having a through-portion (a through-cavity 107); and
a chip stack (stack 110 comprising component 115a, component 115b, and a spacer 410; a stack of chip, paragraph 23) including a first chip (115a) having a rear surface opposite to a front surface on which a connection pad (pad 130) is disposed, and a second chip (a spacer 410 in Fig. 4 or a dummy component 210 in Fig. 2) attached to the rear surface of the first chip (115a) and having a different thickness from the first chip,
wherein at least a portion of the chip stack is disposed in the through-portion (the stack is in 107); and
wherein the second chip includes a dummy (410 is a spacer which is similar to a dummy component; 210 is a dummy component).
Regarding claim 2, Boja discloses the claimed invention as set forth in claim 1. Boja further discloses the first chip includes a silicon capacitor (paragraphs 26 & 27).
Regarding claim 3, Boja discloses the claimed invention as set forth in claim 1. Boja further discloses the first chip (115a) is thicker than the second chip (410).
Regarding claim 4, Boja discloses the claimed invention as set forth in claim 1. Boja further discloses the chip stack further includes an adhesive (the coupling layer 434a; paragraph 43) disposed between the first and second chips.
Regarding claim 5, Boja discloses the claimed invention as set forth in claim 4. Boja further suggests the adhesive includes a die attach film (the film 434a attach the dies 115a and 410 together).
Regarding claim 6, Boja discloses the claimed invention as set forth in claim 1. Boja further suggests the first insulating layer is a layer having a thickness of 1.2 mm or more (the substrate is within 1.2 mm; paragraph 19).
Regarding claim 7, Boja discloses the claimed invention as set forth in claim 1. Boja further discloses first and second wiring layers (the metal layers 102c, 102d, Fig. 4) respectively disposed on an upper surface and a lower surface of the first insulating layer (upper and lower surface of 102a); and a first via layer penetrating (through-vias 119) through the first insulating layer and connecting at least a portion of each of the first and second wiring layers to each other (Fig. 4).
Regarding claim 8, Boja discloses the claimed invention as set forth in claim 7. Boja further discloses a second insulating layer (the insulating layer 116 comprising 116a on the top side, 116b on the bottom side and 116c in the through hole 107) covering at least a portion of each of the first insulating layer (102a) and the chip stack (110) and disposed in at least a portion of the through portion (portion 116c), third (117a) and fourth (117b) wiring layers respectively disposed on an upper surface and a lower surface of the second insulating layer; a second via layer (118a) penetrating through a portion of an upper side of the second insulating layer, and connecting at least a portion of each of the first (102c) and third wiring layers (117a) and at least a portion of each of the first wiring layer and the connection pad (130) to each other; and a third via layer (118b) penetrating through a portion of a lower side of the second insulating layer (116b), and connecting at least a portion of each of the second (102d) and fourth wiring layers (117b) to each other.
Regarding claim 21, Boja, in view of Shin, discloses the claimed invention as set forth in claim 4. Boja further discloses the adhesive is thinner than the first and second chips (Fig. 2 and Fig. 4).
Regarding claim 22, Boja, in view of Shin, discloses the claimed invention as set forth in claim 6. Boja further discloses a thickness of the first insulating layer is substantially the same as a thickness of the chip stack (Fig. 4).
Regarding claim 23, Boja, in view of Shin, discloses the claimed invention as set forth in claim 7. Boja further discloses an upper surface of the first wiring layer (102c) is coplanar with an upper surface of the connection pad (130, Fig. 4).
Regarding claim 24, Boja, in view of Shin, discloses the claimed invention as set forth in claim 1. Boja further discloses one surface of the first insulating layer (102a; Fig. 2) is coplanar with one surface of the second chip (210) located farther from the first chip (Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boja (US 20240222213), in view of Mok (US 11289452).
Regarding claim 9, Boja discloses the claimed invention as set forth in claim 8.
Boja does not explicitly disclose first and second resist layers respectively disposed on an upper surface and a lower surface of the second insulating layer, and having an opening exposing at least a portion of each of the third and fourth wiring layers.
Mok teaches first and second resist layers (top and bottom solder resist layer 19; Fig. 3) respectively disposed on an upper surface and a lower surface of the second insulating layer (the insulating layer below layer 19), and having an opening (the opening for exposing the top and bottom wiring layers for the bonding points 15) exposing at least a portion of each of the third and fourth wiring layers (top and bottom wiring layers covered by the solder resist layer 19).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a solder resist layer when solder is used to bond the chip to the surface of the circuit board in order to prevent short circuit caused by possible solder overflowing.
Regarding claim 10, Boja, in view of Mok, discloses the claimed invention as set forth in claim 9. Mok further suggests a semiconductor chip (the chip on the top and bottom of the substrate connected to the exposed bonding points 15, Fig. 3; see also the chips 31 – 34 in Fig. 6) disposed on the first resist layer and connected to an exposed portion of the third wiring layer (top side chip and solder resist layer).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boja (US 20240222213), in view of Kim (US 10547119).
Regarding claim 11, Boja discloses the claimed invention as set forth in claim 1.
Boja does not explicitly disclose each of the through-portion and the chip stack is provided in plural form, and each of the plurality of chip stacks is at least partially disposed in the plurality of through-portions.
Kim suggests a plurality of packages embedded in the substrate, Fig. 13.
It would have been obvious to one having skill in the art at the effective filing date of the invention to duplicate a working component in order to increase the complexity of the electronic device.
Claim(s) 12 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boja (US 20240222213), in view of Shin (US 6798049).
Regarding claim 12, Boja discloses a printed circuit board, comprising:
a first insulating layer (a monolithic core 102a; Fig. 2) having a through-portion (a through-cavity 107);
a first chip (the chip 115a) disposed at least partially in the through-portion and having a rear surface (bottom surface of 115a) opposite to a front surface (top surface of 115a) on which a connection pad (pad 130) is disposed;
a second chip (a dummy component 210) disposed at least partially in the through-portion (107) and attached to the rear surface of the first chip (115a); and
a second insulating layer (a layer comprising portion 116a, 116b, and 116c) covering at least a portion of the first insulating layer (102a) and each of the first and second chips (115a, 210) and disposed in at least a portion of the through-portion (portion 116c disposed in the cavity 107).
Boja does not explicitly disclose the second chip is rotationally offset from the first chip on a plane.
Shin teaches the second chip (chip 2; Fig. 8B) is rotationally offset from the first chip (chip 1) on a plane.
It would have been obvious to one having skill in the art at the effective filing date of the invention to rearrange the position of components in order to fit all the components into a limited space of a circuit substrate.
Regarding claim 13, Boja, in view of Shin, discloses the claimed invention as set forth in claim 12.
Boja does not explicitly disclose a side surface of the second chip has a step portion from a side surface of the first chip in a cross- section.
Shin teaches a side surface of the second chip (chip 2, Fig. 2C) has a step portion from a side surface of the first chip (chip 1) in a cross- section.
It would have been obvious to one having skill in the art at the effective filing date of the invention to adjust the dimension of the components in order to fit all the components into the limited space of the circuit substrate.
Regarding claim 14, Boja, in view of Shin, discloses the claimed invention as set forth in claim 12. Boja further discloses an adhesive (the coupling layer 134, Fig. 2) disposed between the first and second chips (115a, 210) and attaching the second chip to the rear surface of the first chip.
Regarding claim 15, Boja, in view of Shin, discloses the claimed invention as set forth in claim 12. Boja further discloses each of the first and second chips (silicon base chip; paragraph 30) includes a silicon die, and the adhesive includes a die attach film (adhesive layer 134 attach the silicon chip together).
Regarding claim 16, Boja, in view of Shin, discloses the claimed invention as set forth in claim 12. Boja further discloses first and second wiring layers (the metal layers 102c, 102d) disposed above and below the first insulating layer, respectively; and a first via layer (the through-vias 119) disposed at least partially in the first insulating layer (102a) and connecting at least a portion of each of the first and second wiring layers to each other.
Regarding claim 17, Boja, in view of Shin, discloses the claimed invention as set forth in claim 12. Boja further discloses third and fourth wiring layers (117a, 117b) disposed above and below the second insulating layer (119a, 116b, 116c), respectively; a second via layer (118a) disposed at least partially in an upper side of the second insulating layer (116a), and connecting at least a portion of each of the first (102c) and third wiring layers (117a) and at least a portion of each of the first wiring layer and the connection pad (130) to each other; and a third via layer (118b) disposed at least partially in a lower side of the second insulating layer (116b), and connecting at least a portion of each of the second (102d) and fourth wiring layers (117b) to each other.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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