Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 7, 8 ,9, 11 - 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 10547119).
Regarding claim 1, Kim discloses a printed circuit board, comprising:
a first insulating layer (the support layer 355a, Fig. 7) having a through-portion (the space in the support layer 355a containing chips 301c and 302c);
a chip stack (the chip 301c and 302c) including a first chip (consider chip 302c as the first chip) having a rear surface opposite to a front surface on which a connection pad (the pad on the surface of the chip 302c) is disposed, and a second chip (consider chip 301c as the second chip) attached to the rear surface of the first chip and having a different thickness from the first chip (the thickness of chip 301c and 302c are different), wherein at least a portion of the chip stack is disposed in the through-portion (Fig. 7); and
a second insulating layer (the encapsulant 305a) covering at least a portion of each of the first insulating layer and the chip stack and disposed in at least a portion of the through-portion.
Regarding claim 4, Kim discloses the claimed invention as set forth in claim 1. Kim further discloses the chip stack further includes an adhesive (adhesive 403a, Fig. 4) disposed between the first and second chips.
Regarding claim 5, Kim discloses the claimed invention as set forth in claim 4. Kim further suggests the adhesive includes a die attach film (the adhesive 403a is film to attach two chips).
Regarding claim 7, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests first and second wiring layers respectively disposed on an upper surface and a lower surface of the first insulating layer (the wiring layers on both surfaces of the substrate 355a such wiring layers 320b and 359b; Fig. 6); and a first via layer (via 360a) penetrating through the first insulating layer and connecting at least a portion of each of the first and second wiring layers to each other (Fig. 7).
Regarding claim 8, Kim discloses the claimed invention as set forth in claim 7. Kim further suggests third and fourth wiring layers (other layers on both sides of the substrate 355a) respectively disposed on an upper surface and a lower surface of the second insulating layer; a second via layer (the longer via similar to via 360a on the right side of the substrate 355a connecting the other wiring layers) penetrating through a portion of an upper side of the second insulating layer, and connecting at least a portion of each of the first and third wiring layers and at least a portion of each of the first wiring layer and the connection pad to each other; and a third via layer penetrating through a portion of a lower side of the second insulating layer, and connecting at least a portion of each of the second and fourth wiring layers to each other (Fig. 7 and 8G).
Regarding claim 9, Kim discloses the claimed invention as set forth in claim 8. Kim further suggests first and second resist layers (layer 280i and 305i) respectively disposed on an upper surface and a lower surface of the second insulating layer, and having an opening exposing at least a portion of each of the third and fourth wiring layers (Fig. 9G).
Regarding claim 11, Kim discloses the claimed invention as set forth in claim 1. Kim further suggests each of the through-portion and the chip stack is provided in plural form, and each of the plurality of chip stacks is at least partially disposed in the plurality of through-portions (layers 456a and 455a form a plural through hole stack, Fig. 3).
Regarding claim 12, Kim discloses a printed circuit board, comprising:
a first insulating layer (the core layer 355a, Fig. 6 or 7) having a through-portion (a through portion containing chips 0301c and 301c);
a first chip (consider chip 302c as a first chip) disposed at least partially in the through-portion and having a rear surface opposite to a front surface on which a connection pad (the pads on the surface of the chip 302c) is disposed;
a second chip (the chip 301c) disposed at least partially in the through-portion and attached to the rear surface of the first chip so that an edge of the second chip is offset from the first chip on a plane (Fig. 6 or 7); and
a second insulating layer (the encapsulating layer 305a) covering at least a portion of the first insulating layer and each of the first and second chips and disposed in at least a portion of the through-portion.
Regarding claim 13, Kim discloses the claimed invention as set forth in claim 12. Kim further suggests a side surface of the second chip has a step portion from a side surface of the first chip in a cross-section (Figs. 6 and 7).
Regarding claim 14, Kim discloses the claimed invention as set forth in claim 12. Kim further suggests an adhesive (the adhesive 303b, Fig. 6) disposed between the first and second chips and attaching the second chip to the rear surface of the first chip.
Regarding claim 15, Kim discloses the claimed invention as set forth in claim 14. Kim further suggests each of the first and second chips includes a silicon die (semiconductor chip is understandably a silicon die), and the adhesive includes a die attach film (the adhesive layer 303b is a film attaching IC chips).
Regarding claim 16, Kim discloses the claimed invention as set forth in claim 12. Kim further suggests first and second wiring layers (wiring layer 32b and 359b; Fig. 6) disposed above and below the first insulating layer, respectively; and a first via layer (360a, Fig. 7) disposed at least partially in the first insulating layer and connecting at least a portion of each of the first and second wiring layers to each other.
Regarding claim 17, Kim discloses the claimed invention as set forth in claim 16. Kim further suggests third and fourth wiring layers (other wiring layers on top of the wiring layers in claim 16 such as layer 290) disposed above and below the second insulating layer, respectively; a second via layer (one of the longer via on the side of the substrate 355a) disposed at least partially in an upper side of the second insulating layer, and connecting at least a portion of each of the first and third wiring layers and at least a portion of each of the first wiring layer and the connection pad to each other; and a third via layer (one of the longer via on the side of the substrate 355a) disposed at least partially in a lower side of the second insulating layer, and connecting at least a portion of each of the second and fourth wiring layers to each other.
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (US 20170194266).
Regarding claim 18, Kwon discloses a printed circuit board, comprising:
a first insulating layer (the mold layer 105) having a through-portion (the through hole contain the chip (104);
a stack including a chip (chip 104) having a rear surface opposite to a front surface on which a connection pad (pad 103) is disposed, and a dummy element (the dummy 113) attached to the rear surface of the chip, wherein at least a portion of the stack is disposed in the through-portion; and
a second insulating layer (layer 123) covering at least a portion of each of the first insulating layer and the stack and disposed in at least a portion of the through-portion.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10547119), in view of Mok (US 20210195735).
Regarding claim 2, Kim discloses the claimed invention as set forth in claim 1.
Kim does not explicitly disclose the first chip includes a silicon capacitor.
Kim suggests one of the embedded component is a capacitor (351a, 351a).
Mok suggests the component (7, Fig. 1) in the stack is a capacitor (paragraph 59).
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a capacitor in the circuitry in order to store electrical charge for the circuit.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10547119), in view of Kwon (US 20170194266).
Regarding claim 3, Kim discloses the claimed invention as set forth in claim 2.
Kim does not explicitly disclose the second chip includes a silicon dummy.
Kim suggests a heat sink (390i) that may be considered as a dummy structure.
Kwon teaches a silicon dummy structure (113, paragraph 25) in the stack, Fig. 1A.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include a dummy structure in the circuit board to fill in the space and support other components.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10547119), in view of Boja (US 20240222213).
Regarding claim 6, Kim discloses the claimed invention as set forth in claim 1.
Kim does not explicitly disclose the first insulating layer is a layer having a thickness of 1.2 mm or more.
Boja suggests the substrate in within 1.2 mm (paragraph 19).
It would have been obvious to one having skill in the art at the effective filing date of the invention to select a common thickness of the substrate in order to form a circuit board.
Claim(s) 19, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20170194266 A1), in view of Mok (US 11289452).
Regarding claim 19, Kwon discloses the claimed invention as set forth in claim 18.
Kwon does not explicitly disclose first and second wiring layers respectively disposed on an upper surface and a lower surface of the first insulating layer; a first via layer penetrating through the first insulating layer and connecting at least a portion of each of the first and second wiring layers to each other; third and fourth wiring layers respectively disposed on an upper surface and a lower surface of the second insulating layer; a second via layer penetrating through a portion of an upper side of the second insulating layer, and connecting at least a portion of each of the first and third wiring layers and at least a portion of each of the first wiring layer and the connection pad to each other; and a third via layer penetrating through a portion of a lower side of the second insulating layer, and connecting at least a portion of each of the second and fourth wiring layers to each other.
Mok teaches a core layer having several wiring layers on top side and the bottom side and several different vias with different length to connect the wiring layers together.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include wiring layer and different length of via in order to stack all the connection of the circuitry into the limited space of the circuit substrate.
Regarding claim 20, Kwon, in view of Mok, discloses the claimed invention as set forth in claim 19. Kwon further suggests the dummy element is electrically insulated from the first to fourth wiring layers and the first to third via layers (the dummy layer 113 is not connected to any via or wiring layers).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1, 7, 8, and 9, a combination of limitations that a semiconductor chip disposed on the first resist layer and connected to an exposed portion of the third wiring layer. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Boja (US 20240222213) discloses a stack of chip embedded in a substrate, Fig. 1B.
Mok (US 20210195735) discloses a stack of chip embedded in a substrate, Fig. 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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/BINH B TRAN/Primary Examiner, Art Unit 2848