Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I ( in the reply filed on June 30, 2026, is acknowledged.
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 30, 2026.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claims 1, 17, and 18 each recite the limitation, “at least one upper insulation layer comprising an inorganic material”. However, the detailed description states that the upper insulation layer is organic ([00193]: “The upper insulation layer IL-U includes an organic material.”) and does not disclose the possibility of an inorganic material, thus contradicting the claims.
For examination purposes, it will be assumed that the upper insulation layer comprises an inorganic material, as recited in claims 1, 17, and 18.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation, “a second open area in which either the plurality of readout lines, the plurality of data lines, or both do not overlap with each other”. However, the data lines and readout lines can always be made to overlap depending on what perspective they are viewed from, thus rendering the recited limitation impossible to realize.
For examination purposes, it will be assumed that the readout lines and data lines do not overlap each other from a plan view.
This rejection can be overcome by reciting in claim 13 from what perspective the readout lines and data lines do not appear to overlap each other.
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Fig. 1A of Takahashi, reproduced with annotations added by the examiner.
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Figs. 3A-3F of Takahashi, reproduced with annotations added by the examiner.
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Fig. 4 of Takahashi, reproduced with annotations added by the examiner.
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Alternate reproduction of Fig. 4 of Takahashi, with the first and second open areas labeled.
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Fig. 27 of Takahashi, reproduced with annotations added by the examiner.
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Fig. 37B of Takahashi, reproduced with annotations added by the examiner.
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Fig. 3 of Uchida, reproduced with annotations added by the examiner.
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Fig. 7 of Uchida, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et. al., Pub. No. US 2022/0350432, hereafter referred to as Takahashi, in view of Uchida et. al., Pub. No. US 2021/0012082, hereafter referred to as Uchida.
Regarding claim 1, Takahashi teaches “A display device comprising: a display panel” (Takahashi [0082]; Fig. 1A, display device 10) “comprising: an active area” (Takahashi [0082]; Fig. 1A, display portion 11); “a peripheral area adjacent to the active area” (Takahashi [0082-0083]; Fig. 1A, portion of the substrate 18 where the gate driver circuit 13, row driver circuit 19, IC 20, and FPC 25 are disposed); “a circuit layer comprising a plurality of insulation layers” (Takahashi [0351] and [0354]; Fig. 27, portion of the device below the partition 216 and containing the transistors 201, 205, and 206) “comprising: at least one lower insulation layer” (Takahashi [0359]; Fig. 27, insulating layer 211); “and at least one upper insulation layer comprising an inorganic material” (Takahashi [0352] and [0359]; Fig. 27, insulating layers 214 and 215; also see [0361]: “An inorganic insulating film is preferably used as each of the insulating layer 211, the insulating layer 213, and the insulating layer 215.”; also note that, per the discussion of rejections under 35 U.S.C. 112(b), it is assumed that the upper insulation layers can be either inorganic or organic); “and an element layer” (Takahashi Fig. 27; portion of the device including and above the partition 216) “comprising a plurality of light emitting elements in the active area” (Takahashi [0381]; Fig. 27, light-emitting device 60; also see [0090] and [0103] and Figs. 3A-3F and 4, pixel circuits 14R, 14G, and 14B, collectively pixel circuits 14; note that there are multiple pixel circuits 14 in Fig. 4), “and a plurality of light sensing elements in the active area” (Takahashi [0385]; Fig. 27, light-receiving device 70; also see [0090] and [0104] and Figs. 3A-3F and 4, pixel circuits 15; note that there are multiple pixel circuits 15 in Fig. 4).
However, Takahashi does not teach “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed, and wherein the circuit layer comprises: a plurality of readout lines electrically connected with the plurality of light sensing elements, and extending from the active area to the peripheral area; and an inorganic insulation pattern overlapping with the open area and at least a portion of the plurality of readout lines.” Takahashi, does, however, teach a plurality of readout lines electrically connected to the plurality of light-sensing elements (Takahashi [0122]: “Since the imaging data written to the pixel circuits 15 are output to the wirings 35, the wirings 35 can be regarded as data lines.”; Fig. 4, note that the pixel circuits 15[i, j] are connected to the wirings 35) and that they extend into the peripheral area (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11). Takahashi further shows a transistor electrically connected to a light-receiving device (Takahashi [0351]; Fig. 27, note that the transistor 205 is electrically connected to the light-receiving device 70).
Uchida, on the other hand, teaches a fingerprint detection device (Uchida [0021]: “The detection region AA is a region overlapping a plurality of photodiodes PD (refer to FIG. 4) included in the sensor unit 10.” and [0023]: “The sensor unit 10 is an optical sensor including the photodiodes PD as photoelectric conversion elements.”; Fig. 3, detection region AA and sensor unit 10) including photodiodes (Uchida [0057]; Fig. 7, photodiode PD) disposed over a circuit area (Uchida [0091]; Fig. 7, region of the device below sixth inorganic insulating layer 22f) with signal lines (Uchida [0038] and [0064]; Fig. 3, signal lines SGL1-12 and Fig. 7, source electrode 62; also see [0067]: “A part of the signal line SGL, which overlaps the first semiconductor 61 is the source electrode 62.”). Furthermore, each photodiode is electrically connected to the drain of a transistor within the circuit area (Uchida [0067]; Fig. 7, note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35; also see [0033]: “The first switching element Tr is achieved by a thin film transistor…”) and the source of the same transistor is a signal line (Uchida [0067]; Fig. 7, source electrode 62). Furthermore, Uchida shows a peripheral region (Uchida [0073]; Fig. 7, peripheral region GA) with an open area within which none of the insulating layers in the upper portions of the circuit region extend (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area). In addition, Uchida shows an additional inorganic insulating layer that overlaps a portion of the signal line and an open area (Uchida [0085]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e overlap a small portion of the source electrode 62 from below; also note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area). Uchida further teaches that this device is intended to be incorporated into a display device (Uchida [0102]; Fig. 11, display apparatus 120 and fingerprint detection apparatus 1).
The fingerprint detection apparatus of Uchida can be incorporated into the display device of Takahashi by connecting the signal line to the source of the transistor that is connected to the light receiving element. Furthermore, the peripheral region of Uchida with an open area can be incorporated into the device of Takahashi as a similar open area in which the insulating layer 214 does not extend. Finally, the additional inorganic insulating layer of Uchida can be incorporated into the device of Takahashi as an additional inorganic insulating layer between the transistor 205 and the insulating layer 214. The combined device teaches “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed” (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area), “and wherein the circuit layer comprises: a plurality of readout lines electrically connected with the plurality of light sensing elements” (Uchida [0038] and [0067]; Fig. 3, signal lines SGL1-12, and Fig. 7, source electrode 62; note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35, and that the first switching element Tr is connected to the source electrode 62), “and extending from the active area to the peripheral area” (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11; Uchida Fig. 3; note that the signal lines SGL1-12 extend into the peripheral region); “and an inorganic insulation pattern overlapping with the open area and at least a portion of the plurality of readout lines” (Uchida [0085]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e overlap a small portion of the source electrode 62 from below; also note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the placement of the signal line of Uchida into the device of Takahashi because doing so provides a means for transmitting the signal from the photodetector to external hardware and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include the open area of Uchida in the device of Takahashi because doing so creates a boundary between the display area and the external hardware in the peripheral area and it would be a simple combination of elements of the two disclosures. Finally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included an additional inorganic insulating pattern between the transistor 205 and the insulating layer 214 of Takahashi as suggested by Uchida because doing so would help to provide more separation between the transistor and the light-emitting layer, preventing unwanted crosstalk, and it would have been a simple combination of elements of the two disclosures.
Regarding claim 2, the combined device of Takahashi and Uchida described in the discussion of claim 1 teaches “The display device of claim 1” but does not explicitly teach “wherein: the circuit layer further comprises a first conductive layer under each of the plurality of readout lines; and the inorganic insulation pattern comprises a first inorganic insulation pattern between the plurality of readout lines and the first conductive layer”. Takahashi depicts a transistor connected to a light-receiving device (Takahashi [0351]; Fig. 27, note that the transistor 205 is electrically connected to the light-receiving device 70), but is silent on its structure.
Uchida, on the other hand, does teach “wherein: the circuit layer further comprises a first conductive layer under each of the plurality of readout lines” (Uchida [0070]; Fig. 7, note that the first conductive layer 65 is disposed directly underneath the source electrode 62); “and the inorganic insulation pattern comprises a first inorganic insulation pattern between the plurality of readout lines and the first conductive layer” (Uchida [0071]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e have portions disposed between the first conductive layer 65 and the source electrode 62).
The first conductive layer and fourth inorganic insulating layer of Uchida can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 1 as a conductive electrode on the transistor connected to the source electrode and an inorganic insulating layer between the conductive electrode and the source electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the first conductive layer and fourth inorganic insulating layer of Uchida into the combined device of Takahashi and Uchida described in the discussion of claim 1 because doing so would have allowed for communication between a light-receiving element and the corresponding data line and it would be a simple combination of elements of the two disclosures.
Regarding claim 3, the combination of Takahashi and Uchida described in the discussion of claim 2 further teaches “The display device of claim 2, wherein the first conductive layer is configured to be applied with a constant voltage or ground voltage” (Uchida [0034] and [0043]; Fig. 3; note that the signal lines SGL1-12 are electrically connected to the reference signal line Lvr, which provides a reference signal VR1; also see [0070] and Fig. 7 and note that the source electrode 62 is in contact with the first conductive layer 65, and thus the first conductive layer 65 also receives the reference signal VR1).
Regarding claim 4, the combination of Takahashi and Uchida described in the discussion of claim 2 teaches “The display device of claim 2” but does not teach “wherein the inorganic insulation pattern further comprises a second inorganic insulation pattern over the plurality of readout lines.”
Uchida, on the other hand, does teach “wherein the inorganic insulation pattern further comprises a second inorganic insulation pattern over the plurality of readout lines” (Uchida [0062]; Fig. 7, note that the sixth inorganic insulating layer 22f is disposed above the source electrode 62).
The sixth inorganic insulating layer of Uchida can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 2 as an additional insulating layer disposed over the upper insulating layer and partially covering the light-receiving element.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced a second inorganic insulating layer disposed over the upper insulating layer and partially covering the light-receiving element because it would provide further protection of the electrical connections between the light-receiving element and the other elements in the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 16, the combination of Takahashi and Uchida described in the discussion of claim 1 teaches “The display device of claim 1” but does not teach “wherein: the peripheral area further comprises a bending area bent about a bending axis parallel to one direction; and the open area is located between the active area and the bending area.”
Takahashi, on the other hand, shows an embodiment of their invention (Takahashi Fig. 37B) with a portion of a display panel outside of the display area that is folded back (Takahashi [0615]; Fig. 37B, note that a portion of the display panel 6511 is folded back), with external circuitry attached to the folded back portion (Takahashi [0615]; Fig. 37B, note that the IC 6516, FPC 6515, and printed circuit board 6517 are attached to the folded back portion of the display panel 6511; also see [0082] and Fig. 1A, display device 10 and display portion 11).
The folded area shown in Takahashi can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 1 by introducing a bending area between the open area and the external circuitry. The combined device teaches “wherein: the peripheral area further comprises a bending area bent about a bending axis parallel to one direction” (Takahashi [0615]; Fig. 37B, note that a portion of the display panel 6511 is folded back along an axis going into and out of the page); “and the open area is located between the active area and the bending area” (Takahashi [0615]; note that the IC 6516, FPC 6515, and printed circuit board 6517 are attached to the folded back portion of the display panel 6511; also note that a portion of the display panel 6511 outside of the display area 6502 is not in the bending area).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a bending area as taught by Takahashi in the combined device of Takahashi and Uchida described in the discussion of claim 1 because doing so would help to make a device including the display panel smaller and it would be a simple combination of elements of the two disclosures.
Regarding claim 18, Takahashi teaches “A display device comprising: a display panel” (Takahashi [0082]; Fig. 1A, display device 10) “comprising: an active area” (Takahashi [0082]; Fig. 1A, display portion 11); “a peripheral area adjacent to the active area” (Takahashi [0082-0083]; Fig. 1A, portion of the substrate 18 where the gate driver circuit 13, row driver circuit 19, IC 20, and FPC 25 are disposed); “a circuit layer comprising a plurality of insulation layers” (Takahashi [0351] and [0354]; Fig. 27, portion of the device below the partition 216 and containing the transistors 201, 205, and 206) “comprising: at least one lower insulation layer” (Takahashi [0359]; Fig. 27, insulating layer 211); “and at least one upper insulation layer comprising an inorganic material” (Takahashi [0352] and [0359]; Fig. 27, insulating layers 214 and 215; also see [0361]; also note that, per the discussion of rejections under 35 U.S.C. 112(b), it is assumed that the upper insulation layers can be either inorganic or organic); “and an element layer” (Takahashi Fig. 27; portion of the device including and above the partition 216) “comprising a plurality of light emitting elements in the active area” (Takahashi [0381]; Fig. 27, light-emitting device 60; also see [0090] and [0103] and Figs. 3A-3F and 4, pixel circuits 14R, 14G, and 14B, collectively pixel circuits 14; note that there are multiple pixel circuits 14 in Fig. 4), “and a plurality of light sensing elements in the active area” (Takahashi [0385]; Fig. 27, light-receiving device 70; also see [0090] and [0104] and Figs. 3A-3F and 4, pixel circuits 15; note that there are multiple pixel circuits 15 in Fig. 4).
Takahashi, however, does not teach “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed, and wherein the circuit layer comprises: a plurality of readout lines electrically connected with the plurality of light sensing elements, and extending from the active area to the peripheral area; and an inorganic insulation pattern overlapping with the open area, and contacting at least one of a top surface or a bottom surface of the plurality of readout lines.” Takahashi, does, however, teach a plurality of readout lines electrically connected to the plurality of light-sensing elements (Takahashi [0122]; Fig. 4, note that the pixel circuits 15[i, j] are connected to the wirings 35) and that they extend into the peripheral area (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11). Takahashi further shows a transistor electrically connected to a light-receiving device (Takahashi [0351]; Fig. 27, note that the transistor 205 is electrically connected to the light-receiving device 70).
Uchida, on the other hand, teaches a fingerprint detection device (Uchida [0021]: “The detection region AA is a region overlapping a plurality of photodiodes PD (refer to FIG. 4) included in the sensor unit 10.” and [0023]: “The sensor unit 10 is an optical sensor including the photodiodes PD as photoelectric conversion elements.”; Fig. 3, detection region AA and sensor unit 10) including photodiodes (Uchida [0057]; Fig. 7, photodiode PD) disposed over a circuit area (Uchida [0091]; Fig. 7, region of the device below sixth inorganic insulating layer 22f) with signal lines (Uchida [0038] and [0064]; Fig. 3, signal lines SGL1-12 and Fig. 7, source electrode 62; also see [0067]). Furthermore, each photodiode is electrically connected to the drain of a transistor within the circuit area (Uchida [0067]; Fig. 7, note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35; also see [0033]) and the source of the same transistor is a signal line (Uchida [0067]; Fig. 7, source electrode 62). Furthermore, Uchida shows a peripheral region (Uchida [0073]; Fig. 7, peripheral region GA) with an open area within which none of the insulating layers in the upper portions of the circuit region extend (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area). In addition, Uchida shows a pair of inorganic insulating layers that is in contact with a bottom surface of the signal line (Uchida [0062]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e contact a bottom surface of the signal line 62) and overlaps with the open area (Uchida [0085]: “A contact hole H6 is provided through the third inorganic insulating layer 22c, the fourth inorganic insulating layer 22d, the fifth inorganic insulating layer 22e, and a first organic insulating layer 23.”; also see Fig. 7 and note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area). Uchida further teaches that this device is intended to be incorporated into a display device (Uchida [0102]; Fig. 11, display apparatus 120 and fingerprint detection apparatus 1).
The fingerprint detection apparatus of Uchida can be incorporated into the display device of Takahashi by connecting the signal line to the source of the transistor that is connected to the light receiving element. Furthermore, the peripheral region of Uchida with an open area can be incorporated into the device of Takahashi as a similar open area in which the insulating layer 214 does not extend. Finally, the fourth inorganic insulating layer of Uchida can be incorporated into the device of Takahashi as an additional inorganic insulating layer directly contacting the source of the transistor 205 and with a via to allow the signal line to be electrically connected to the source. The combined device teaches “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed” (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area), “and wherein the circuit layer comprises: a plurality of readout lines electrically connected with the plurality of light sensing elements” (Uchida [0038] and [0067]; Fig. 3, signal lines SGL1-12, and Fig. 7, source electrode 62; note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35, and that the first switching element Tr is connected to the source electrode 62), “and extending from the active area to the peripheral area” (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11; Uchida Fig. 3; note that the signal lines SGL1-12 extend into the peripheral region); “and an inorganic insulation pattern overlapping with the open area” (Uchida [0085]; Fig. 7, fourth and fifth inorganic insulating layers 22d and 22e; note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area), “and contacting at least one of a top surface or a bottom surface of the plurality of readout lines” (Uchida [0062]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e contact a bottom surface of the signal line 62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the placement signal line of Uchida into the device of Takahashi because doing so provides a means for transmitting the signal from the photodetector to external hardware and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include the open area of Uchida in the device of Takahashi because doing so creates a boundary between the display area and the external hardware in the peripheral area and it would be a simple combination of elements of the two disclosures. Finally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included an additional inorganic insulating layer disposed directly over the source of the transistor 205 of Takahashi and with a via to allow the source electrode to be electrically connected to the source as suggested by Uchida because the insulating layer would provide some amount of separation between the source and the source line and it would have been a simple combination of elements of the two disclosures.
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Fig. 7 of Bang, reproduced with annotations added by the examiner.
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Fig. 12 of Bang, reproduced with annotations added by the examiner.
Claims 4-7, 9-11, 15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi and Uchida in view of Bang, Pub. No. US 2021/0149524, hereafter referred to as Bang.
Regarding claim 4, the combined device of Takahashi and Uchida described in the discussion of claim 2 teaches “The display device of claim 2” but does not teach “wherein the inorganic insulation pattern further comprises a second inorganic insulation pattern over the plurality of readout lines.”
Bang, on the other hand, teaches a device that uses a capacitive method for incorporating touch sensing (Bang [0125]; Fig. 7, touch electrodes TE1-1 to TE1-4 and TE2-1 to TE2-5) in which the readout lines (Bang [0125]; Fig. 7, touch signal lines SL1-1 to SL1-4 and SL2-1 to SL2-5) have a double wire structure (Bang [0127]; Fig. 12 first metal wire SL2-51 and second metal wire SL2-52) in which the two wires are separated by an inorganic insulating layer (Bang [0128]; Fig. 12, first insulating layer TS-IL1; also see [0110]: “…the first insulating layer TS-IL1… may include an inorganic material”). In addition, Bang teaches that this double wire structure reduces the resistance of the wiring (Bang [0131]: “When the wire portion TW has the double wire structure, in which the first metal wires SL1-11 to SL1-41 and SL2-11 to SL2-51 and the second metal wires SL1-12 to SL1-42 and SL2-12 to SL2-52 are stacked, a resistance of the wire portion TW may be reduced.”).
The double wire structure with an insulating layer taught by Bang can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 2 by making the signal line in said combined device with a double wire structure, with the two wires separated by an insulating layer. The combined device teaches “wherein the inorganic insulation pattern further comprises a second inorganic insulation pattern over the plurality of readout lines” (Uchida [0067]; Fig. 7, source electrode 62; Bang [0128]; Fig. 12, first insulating layer TS-IL1; note that this additional insulating layer would be disposed over the source electrode 62 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the double wire structure for the readout line of Bang into the combined device of Takahashi and Uchida because the double wire structure would reduce the resistance of the readout line and it would be a simple combination of elements of the two disclosures.
Regarding claim 5, the combination of Takahashi, Uchida, and Bang described in the discussion of claim 4 further teaches “The display device of claim 4, wherein: the first inorganic insulation pattern is directly on the first conductive layer” (Uchida [0071]; Fig. 7, note that the fourth insulating layer 22d, treated here as part of the first inorganic insulation pattern, directly contacts the first conductive layer 65); “the plurality of readout lines are directly on the first inorganic insulation pattern” (Uchida [0072]; Fig. 7, note that the source contact 62 directly contacts the fifth insulating layer 22e, treated here as part of the first inorganic insulation pattern); “and the second inorganic insulation pattern is directly on the plurality of readout lines” (Bang [0128]; Fig. 12, first insulating layer TS-IL1; also see [0110]).
Regarding claim 6, the combination of Takahashi and Uchida as applied to claim 4 above teaches “The display device of claim 4” but does not teach “wherein: the circuit layer further comprises a second conductive layer over each of the plurality of readout lines; and the second inorganic insulation pattern is located between the plurality of readout lines and the second conductive layer.”
Bang, on the other hand, teaches a display device (Bang Fig. 12) with capacitive touch sensing hardware (Bang [0126]: “The first touch signal lines SL1-1 to SL1-4 and the second touch signal lines SL2-1 to SL2-5 connect between the touch electrode TE and the touch pad TS-PD, and may form the wire portion TW.”; Fig. 12, touch electrode TE and signal line SL2-5; also see [0127]: “…the wire portion TW may have a double wire structure, in which first metal wires SL1-11 to SL1-41 and SL2-11 to SL2-51 and second metal wires SL1-12 to SL1-42 and SL2-12 to SL2-52 are stacked.” and [0128]; Fig. 12, wire portion TW, first metal wire SL2-51, first insulating layer TS-IL1, second metal wire SL2-52, second insulting layer TS-IL2) disposed on the top of the display device, above the light emitting elements (Bang [0126] and [0173]; Fig. 12, note that the touch electrodes TE and wire portion TW are disposed above the layer containing the organic film OL and the first electrode EL1).
The touch sensing hardware of Bang can be incorporated into the combined device of Takahashi and Uchida as applied to claim 4 above by incorporating touch electrodes and touch signal lines, along with the associated insulating layers, disposed above the element layer of the display device. The combined device teaches “wherein: the circuit layer further comprises a second conductive layer over each of the plurality of readout lines” (Bang [0126-0128]; Fig. 12, wire portion TW, first metal wire SL2-51, first insulating layer TS-IL1, second metal wire SL2-52, second insulting layer TS-IL2); “and the second inorganic insulation pattern is located between the plurality of readout lines and the second conductive layer” (Uchida [0062] and [0070]; Fig. 7, sixth inorganic insulating layer 22f and source electrode 62; Bang [0126-0128]; Fig. 12, wire portion TW, first metal wire SL2-51, first insulating layer TS-IL1, second metal wire SL2-52, second insulting layer TS-IL2; note that the sixth inorganic insulating layer 22f of Uchida would be located between the source electrode 62 of Uchida and the wire portion TW of Bang in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated touch sensing hardware as taught by Bang into the combined device of Takahashi and Uchida as applied to claim 4 above because doing so would add touch capability to the device in addition to the existing fingerprint sensing capability and it would be a simple combination of elements of the disclosures.
Regarding claim 7, the combination of Takahashi, Uchida, and Bang described in the discussion of claim 4 further teaches “The display device of claim 6, wherein the second conductive layer is configured to be applied with a constant voltage or ground voltage” (Uchida [0034] and [0043]; Fig. 3; note that the signal lines SGL1-12 are electrically connected to the reference signal line Lvr, which provides a reference signal VR1; also see [0070] and Fig. 7 and note that the source electrode 62 is in contact with the first conductive layer 65, and thus the first conductive layer 65 also receives the reference signal VR1; Bang [0127]; Fig. 12, note that the second metal wire SL2-52 is electrically connected to the source electrode 62 of Uchida in the combined device, and thus also receives the reference signal VR1).
Regarding claim 9, the combination of Takahashi, Uchida, and Bang described in the discussion of claim 6 teaches “The display device of claim 6”, but does not teach “wherein the display panel further comprises an encapsulation layer on the element layer, and covering the plurality of light emitting elements and the plurality of light sensing elements, and wherein the encapsulation layer is located on the second conductive layer in the open area.” Takahashi instead teaches a space disposed over the light-emitting and light-receiving elements (Takahashi [0352]; Fig. 27, space 443) that is filled with an inert gas (Takahashi [0352]: “In FIG. 27, a space 443 surrounded by the substrate 452, the adhesive layer 442, and the insulating layer 214 is filled with an inert gas (e.g., nitrogen or argon), that is, a hollow sealing structure is employed.”).
Uchida, on the other hand, teaches an insulating layer disposed over the photodiode (Uchida [0062]; Fig. 7, note that the second organic insulating layer 23b covers the photodiode PD) and above the signal line (Uchida [0067] and [0071]; Fig. 7, note that the second organic insulating layer 23b is disposed above the source electrode 62), which may function as an encapsulating layer.
The second organic insulating layer of Uchida can be incorporated into the combined device of Takahashi, Uchida, and Bang as applied to claim 4 above by replacing the space of Takahashi with an organic insulator. The combined device teaches “wherein the display panel further comprises an encapsulation layer on the element layer” (Uchida [0062]; Fig. 7, second organic insulating layer 23b), “and covering the plurality of light emitting elements and the plurality of light sensing elements” (Uchida [0062]; Fig. 7, note that the second organic insulating layer 23b covers the photodiode PD and is disposed above the source electrode 62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have replaced the space of the combined device of Takahashi, Uchida, and Bang as applied to claim 4 above with an encapsulation layer made of an insulator as taught by Uchida because an insulator can serve the same purpose of providing insulation between the light-emitting and light-receiving elements and the outside environment as an inert gas-filled space and it would be a simple substitution of one element for another.
The combination of Takahashi, Uchida, and Bang just described, however, does not teach “wherein the encapsulation layer is located on the second conductive layer in the open area.”
Bang, on the other hand, shows an encapsulation area (Bang [0190]; Fig. 12, encapsulation layer TFE) that overlaps with the wire portion (Bang [0190-0191]; Fig. 12, note that the first and third encapsulation layers ENC1 and ENC3 are disposed underneath the first and second metal wires SL2-51 and SL2-52) in an open area (Bang [0172]; Fig. 12, note that the pixel definition film PDL does not extend into the open area).
The extension of the encapsulation layer into the open area of Bang can be incorporated into the combined device of Takahashi, Uchida, and Bang described above by extending the encapsulation area of said combined device into the open area such that it covers the wire portion. The combined device teaches “wherein the encapsulation layer is located on the second conductive layer in the open area” (Uchida [0062]; Fig. 7, second organic insulating layer 62; Bang [0190-0191]; Fig. 12, encapsulation layer TFE; note that the second organic insulating layer 62 of Uchida extends into the open area and overlaps the source electrode 62 and the wire portion TW in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to extend the encapsulation layer of the combined device of Takahashi, Uchida, and Bang described above into the open area as taught by Bang because doing so would help further protect the electronic components of the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 10, the combination of Takahashi, Uchida, and Bang described in the discussion of claim 9 further teaches “The display device of claim 9, wherein the display panel further comprises a sensor layer directly on the encapsulation layer, and comprising at least one sensor conductive layer” (Bang [0126]; Fig. 12, touch electrodes TE).
Regarding claim 11, the combination of Takahashi, Uchida, and Bang as applied to claim 9 above further teaches “The display device of claim 10, wherein the second conductive layer is located between at least a portion of the sensor conductive layer and the plurality of readout lines” (Uchida [0070]; Fig. 7, source electrode 62; Bang [0126-0128]; Fig. 12, note that the touch electrode TE is disposed on top of the first insulating layer TS-IL1, while the first metal wire SL2-51 is disposed below the first insulating layer TS-IL1; note that the first metal wire SL2-51 of Bang is disposed above the source electrode 62 of Uchida in the combined device).
Regarding claim 15, the combination of Takahashi and Uchida described in the discussion of claim 1 teaches “The display device of claim 1” but does not teach “wherein the circuit layer further comprises a dam structure overlapping with the open area, and comprising at least one layer comprising the same material as that of the upper insulation layer.”
Bang, on the other hand, does teach “wherein the circuit layer further comprises a dam structure overlapping with the open area” (Bang [0115] and [0172]; Fig. 12, protrusion member DAM; note that the protrusion member DAM is in an open area wherein the pixel definition layer PDL does not extend), “and comprising at least one layer comprising the same material as that of the upper insulation layer” (Bang [0165] and [0189]: “For example, when the lower protrusion portion DAM1-B and the base protrusion portion DAM2-U include the same material and are formed through the same process as the first via film VIA1…”; Fig. 12, first via film VIA1, lower protrusion member DAM1-B and base protrusion member DAM2-U). Bang further teaches that the dam structure prevents organic material from spilling out to the outside (Bang [0119]: “For example, the first protrusion member DAM1 may prevent organic monomer from being formed by coating the organic thin films from flowing to the outside.”)
The dam structure of Bang can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 1 by including a similar dam structure surrounding the display area.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a dam structure as taught by Bang in the combined device of Takahashi and Uchida described in the discussion of claim 1 because doing so would prevent organic material used in the formation of the device from spilling out during the manufacturing process and it would be a simple combination of elements of the disclosures.
Regarding claim 19, the combination of Takahashi and Uchida described in the discussion of claim 18 teaches “The display device of claim 18, wherein: the circuit layer further comprises a first conductive layer under each of the plurality of readout lines” (Uchida [0070]; Fig. 7, note that the first conductive layer 65 is disposed directly underneath the source electrode 62); “and the inorganic insulation pattern comprises: a first inorganic insulation pattern between the plurality of readout lines and the first conductive layer” (Uchida [0071]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e have portions disposed between the first conductive layer 65 and the source electrode 62); but does not teach “and a second inorganic insulation pattern over the plurality of readout lines.”
Bang, on the other hand, teaches a device that uses a capacitive method for incorporating touch sensing (Bang Figs. 7-13) in which the readout lines (Bang [0125]; Fig. 12, second touch signal line SL2-5) have a double wire structure (Bang [0127]; Fig. 12 first metal wire SL2-51 and second metal wire SL2-52) in which the two wires are separated by an inorganic insulating layer (Bang [0128]; Fig. 12, first insulating layer TS-IL1; also see [0110]: “…the first insulating layer TS-IL1… may include an inorganic material”). In addition, Bang teaches that this double wire structure reduces the resistance of the wiring (Bang [0131]: “When the wire portion TW has the double wire structure, in which the first metal wires SL1-11 to SL1-41 and SL2-11 to SL2-51 and the second metal wires SL1-12 to SL1-42 and SL2-12 to SL2-52 are stacked, a resistance of the wire portion TW may be reduced.”).
The double wire structure with an insulating layer taught by Bang can be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 2 by making the signal line in said combined device with a double wire structure, with the two wires separated by an insulating layer. The combined device teaches “and a second inorganic insulation pattern over the plurality of readout lines” (Uchida [0067]; Fig. 7, source electrode 62; Bang [0128]; Fig. 12, first insulating layer TS-IL1; note that this additional insulating layer would be disposed over the source electrode 62 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the double wire structure for the readout line of Bang into the combined device of Takahashi and Uchida because the double wire structure would reduce the resistance of the readout line and it would be a simple combination of elements of the two disclosures.
Regarding claim 20, the combination of Takahashi, Uchida, and Bang described in the discussion of claim 19 further teaches “The display device of claim 19, wherein: the first inorganic insulation pattern is directly on the first conductive layer” (Uchida [0071]; Fig. 7, note that the fourth insulating layer 22d, treated here as part of the first inorganic insulation pattern, directly contacts the first conductive layer 65); “the plurality of readout lines are directly on the first inorganic insulation pattern” (Uchida [0072]; Fig. 7, note that the source contact 62 directly contacts the fifth insulating layer 22e, treated here as part of the first inorganic insulation pattern); “and the second inorganic insulation pattern is directly on the plurality of readout lines” (Bang [0128]; Fig. 12, first insulating layer TS-IL1; also see [0110]).
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Figure 1: Fig. 1 of Ka, reproduced with annotations added by the examiner.
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Fig. 4 of Ka, reproduced with annotations added by the examiner.
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Fig. 5 of Ka, reproduced with annotations added by the examiner.
Claims 12-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi and Uchida in view of Ka et. al., Pub. No. US 2018/0069068, hereafter referred to as Ka.
Regarding claim 12, the combination of Takahashi and Uchida described in the discussion of claim 2 teaches “The display device of claim 2”, but does not teach “wherein: the circuit layer further comprises a plurality of data lines electrically connected to the plurality of light emitting elements, and extending to the peripheral area; and the first conductive layer is located between the plurality of readout lines and the plurality of data lines.” Takahashi, however, does teach data lines electrically connected to the light-emitting elements (Takahashi [0105]; Fig. 4, note that the wirings 33 are connected to the pixel circuits 14; also see [0118]: “Image data represented by the digital image signal GS_D is supplied to the pixels 12 through the wirings 33; thus, the wirings 33 can be regarded as data lines.”) that extend into a peripheral area (Takahashi [0105]; Fig. 4, note that the wirings 33 connect to data driver circuit 23, which is in the peripheral area). Furthermore, note that the data lines and the readout lines in Takahashi are parallel (Takahashi [0105]; Fig. 4, note that the wirings 33 and the wirings 34 are parallel).
Ka, on the other hand, teaches a similar device (Ka Fig. 1) with data lines (Ka [0073]; Fig. 1, data lines 271), each disposed on the same layer as the source and drain electrodes of a transistor (Ka [0075-0076]; Fig. 4, driving TFT 20, driving source electrode 276, and driving drain electrode 277; note that the data line 271, driving source electrode 276, and driving drain electrode 277 are all disposed directly on top of the insulating interlayer 260) and between the transistor and a light sensor (Ka [0091]; Fig. 4, sensing TFT 30).
The placement of the data line of Ka may be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 2 by placing the data line between the light-sensing element 60 and the light-receiving element 70 in said combined device. The combined device just described teaches “wherein: the circuit layer further comprises a plurality of data lines electrically connected to the plurality of light emitting elements, and extending to the peripheral area” (Takahashi [0105]; Fig. 4, note that the wirings 33 are connected to the pixel circuits 14 and to the data driver circuit 23, which is in the peripheral area; Ka [0075-0076]; Fig. 1, data lines 271, and Fig. 4, driving TFT 20, driving source electrode 276, and driving drain electrode 277; note that the data line 271, driving source electrode 276, and driving drain electrode 277 are all disposed directly on top of the insulating interlayer 260); “and the first conductive layer is located between the plurality of readout lines and the plurality of data lines” (Uchida Fig. 7, first conductive layer 65 and source electrode 62; Ka Fig. 4, data line 271; note that there is a portion of the first conductive layer 65 to the right of the source electrode 62, which will be between the source electrode 62 of Uchida and the data line 271 of Ka in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the placement of the data line of Ka into the combined device of Takahashi and Uchida described in the discussion of claim 2 because doing so would allow for an electrical connection between the data line and the corresponding light-emitting element and it would be a simple combination of elements of the two disclosures.
Regarding claim 13, the combined device of Takahashi, Uchida, and Ka described in the discussion of claim 12 teaches “The display device of claim 12, wherein the open area comprises: a first open area in which the plurality of readout lines overlap with the plurality of data lines” (Takahashi [0107]: “Thus, a signal supplied to the pixels 12 through the wirings 31 can be regarded as a scan signal, and the wirings 31 can be regarded as scan lines.” and [0122]; Fig. 4; wirings 31 and 35; note that the wirings 31 are included here as part of the data lines; also note that the wirings 31 and 35 intersect one another within the first open area); “and a second open area in which either the plurality of readout lines, the plurality of data lines, or both do not overlap with each other” (Takahashi [0122]; Fig. 4, note that the wirings 35 do not overlap one another from a plan view within the second open area), but does not teach “and wherein the inorganic insulation pattern overlaps with the first open area.”
Ka, on the other hand, shows an insulation layer (Ka [0076]; Fig. 5, gate insulating layer 240) that is disposed within the circuit region (Ka [0076] and [0078]; Fig. 5, note that the gate insulating layer 240 extends between a semiconductor layer 232 and a gate electrode 255 on driving TFT 20) that extends into the open area and to a region where a readout line (Ka [0056] and [0076]; Fig. 5, note that the gate insulating layer 240 overlaps the output line 437) connects to external circuitry (Ka [0046] and [0076]; Fig. 5, note that the gate insulating layer 240 overlaps the first sensor driver 921).
The extent of the insulating layer of Ka can be incorporated into the combined device of Takahashi, Uchida, and Ka described in the discussion of claim 12 by extending one of the inorganic insulating layers (Uchida [0071]; Fig. 7, fourth inorganic insulating layer 22d) to extend such that it overlaps the readout line and external circuitry. The combined device teaches “and wherein the inorganic insulation pattern overlaps with the first open area” (Ka [0046], [0056], [0076], and [0078]; Fig. 5, note that the gate insulating layer 240 extends between a semiconductor layer 232 and a gate electrode 255 on driving TFT 20 and overlaps the output line 437 and the first sensor driver 921).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have extended one of the inorganic insulating layers in the circuit area to overlap the open area as taught by Ka in the combined device of Takahashi, Uchida, and Ka described in the discussion of claim 12 because it would have helped to further protect the electronic components from the outside environment and it would be a simple combination of elements of the two disclosures.
Regarding claim 14, the combination of Takahashi, Uchida, and Ka described in the discussion of claim 12 teaches “The display device of claim 12” but does not teach “wherein the plurality of data lines are covered by the lower insulation layer.”
Ka, on the other hand, does teach “wherein the plurality of data lines are covered by the lower insulation layer” (Ka [0070] and [0073]; Fig. 4, note that the buffer layer 220 passes underneath the data line 271).
The passage of the buffer layer underneath the data line shown by Ka can be incorporated into the combined device of Takahashi, Uchida, and Ka described in the discussion of claim 12 by having the lower insulation layer (Takahashi [0359]; Fig. 27, insulating layer 211) pass underneath the data line in said combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the lower insulating layer pass underneath the data line as taught by Ka in the combined device of Takahashi, Uchida, and Ka described in the discussion of claim 12 because it would be a natural consequence of forming the buffer layer before any of the circuitry in the device and it would be a simple combination of elements of the two disclosures.
Regarding claim 17, Takahashi teaches “A display device comprising: a display panel” (Takahashi [0082]; Fig. 1A, display device 10) “comprising: an active area” (Takahashi [0082]; Fig. 1A, display portion 11); “a peripheral area adjacent to the active area” (Takahashi [0082-0083]; Fig. 1A, portion of the substrate 18 where the gate driver circuit 13, row driver circuit 19, IC 20, and FPC 25 are disposed); “a circuit layer comprising a plurality of insulation layers” (Takahashi [0351] and [0354]; Fig. 27, portion of the device below the partition 216 and containing the transistors 201, 205, and 206) “comprising: at least one lower insulation layer” (Takahashi [0359]; Fig. 27, insulating layer 211); “and at least one upper insulation layer comprising an inorganic material” (Takahashi [0352] and [0359]; Fig. 27, insulating layers 214 and 215; also see [0361]; also note that, per the discussion of rejections under 35 U.S.C. 112(b), it is assumed that the upper insulation layers can be either inorganic or organic); “and an element layer” (Takahashi Fig. 27; portion of the device including and above the partition 216) “comprising a plurality of light emitting elements in the active area” (Takahashi [0381]; Fig. 27, light-emitting device 60; also see [0090] and [0103] and Figs. 3A-3F and 4, pixel circuits 14R, 14G, and 14B, collectively pixel circuits 14; note that there are multiple pixel circuits 14 in Fig. 4), “and a plurality of light sensing elements in the active area” (Takahashi [0385]; Fig. 27, light-receiving device 70; also see [0090] and [0104] and Figs. 3A-3F and 4, pixel circuits 15; note that there are multiple pixel circuits 15 in Fig. 4).
Takahashi, however, does not teach “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed, and wherein the circuit layer comprises: a plurality of data lines electrically connected to the plurality of light emitting elements, and extending to the peripheral area; a plurality of readout lines electrically connected with the plurality of light sensing elements, and extending from the active area to the peripheral area; and an inorganic insulation pattern overlapping with the open area, and at least a portion of the inorganic insulation pattern is located between the plurality of data lines and the plurality of readout lines.” Takahashi, does, however, teach a plurality of data lines electrically connected to the light-emitting pixels (Takahashi [0118]; Fig. 4, note that the wirings 33 are connected to the pixel circuits 14[i, j]) that extend into the peripheral area (Takahashi Fig. 4; note that the wirings 33 extend outside the display portion 33) and a plurality of readout lines electrically connected to the plurality of light-sensing elements (Takahashi [0122]; Fig. 4, note that the pixel circuits 15[i, j] are connected to the wirings 35) that extend into the peripheral area (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11). Takahashi further shows a transistor electrically connected to a light-receiving device (Takahashi [0351]; Fig. 27, note that the transistor 205 is electrically connected to the light-receiving device 70).
Uchida, on the other hand, teaches a fingerprint detection device (Uchida [0021]: “The detection region AA is a region overlapping a plurality of photodiodes PD (refer to FIG. 4) included in the sensor unit 10.” and [0023]: “The sensor unit 10 is an optical sensor including the photodiodes PD as photoelectric conversion elements.”; Fig. 3, detection region AA and sensor unit 10) including photodiodes (Uchida [0057]; Fig. 7, photodiode PD) disposed over a circuit area (Uchida [0091]; Fig. 7, region of the device below sixth inorganic insulating layer 22f) with signal lines (Uchida [0038] and [0064]; Fig. 3, signal lines SGL1-12 and Fig. 7, source electrode 62; also see [0067]). Furthermore, each photodiode is electrically connected to the drain of a transistor within the circuit area (Uchida [0067]; Fig. 7, note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35; also see [0033]) and the source of the same transistor is a signal line (Uchida [0067]; Fig. 7, source electrode 62). Furthermore, Uchida shows a peripheral region (Uchida [0073]; Fig. 7, peripheral region GA) with an open area within which none of the insulating layers in the upper portions of the circuit region extend (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area). In addition, Uchida shows a pair of inorganic insulating layers that is in contact with a bottom surface of the signal line (Uchida [0062]; Fig. 7, note that the fourth and fifth inorganic insulating layers 22d and 22e contact a bottom surface of the signal line 62) and overlaps with the open area (Uchida [0085]: “A contact hole H6 is provided through the third inorganic insulating layer 22c, the fourth inorganic insulating layer 22d, the fifth inorganic insulating layer 22e, and a first organic insulating layer 23.”; also see Fig. 7 and note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area). Uchida further teaches that this device is intended to be incorporated into a display device (Uchida [0102]; Fig. 11, display apparatus 120 and fingerprint detection apparatus 1).
The fingerprint detection apparatus of Uchida can be incorporated into the display device of Takahashi by connecting the signal line to the source of the transistor that is connected to the light receiving element. Furthermore, the peripheral region of Uchida with an open area can be incorporated into the device of Takahashi as a similar open area in which the insulating layer 214 does not extend. Finally, the fourth inorganic insulating layer of Uchida can be incorporated into the device of Takahashi as an additional inorganic insulating layer directly contacting the source of the transistor 205 and with a via to allow the signal line to be electrically connected to the source. The combined device teaches “wherein the peripheral area comprises an open area in which the at least one upper insulation layer is not disposed” (Uchida [0057] and [0069-0072] Fig. 7, open area; note that the organic insulating layer 23a does not extend into the open area), “and wherein the circuit layer comprises: …a plurality of readout lines electrically connected with the plurality of light sensing elements” (Uchida [0038] and [0067]; Fig. 3, signal lines SGL1-12, and Fig. 7, source electrode 62; note that the photodiode PD is connected to the drain electrode 63 of the first switching element Tr through the lower electrode 35, and that the first switching element Tr is connected to the source electrode 62), “and extending from the active area to the peripheral area” (Takahashi Fig. 4; note that the wirings 35 extend outside the display portion 11); “and an inorganic insulation pattern overlapping with the open area” (Uchida [0085]; Fig. 7, fourth and fifth inorganic insulating layers 22d and 22e; note that a layer drawn as separate from the fourth inorganic insulating layer 22d is disposed between the third and fifth inorganic insulating layers 22c and 22e next to the contact hole H6, and is thus meant to be part of the fourth inorganic insulating layer 22d, and that small portions of the fourth and fifth inorganic insulating layers 22d and 22e are inside the open area).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the placement of the signal line of Uchida into the device of Takahashi because doing so provides a means for transmitting the signal from the photodetector to external hardware and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include the open area of Uchida in the device of Takahashi because doing so creates a boundary between the display area and the external hardware in the peripheral area and it would be a simple combination of elements of the two disclosures. Finally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included an additional inorganic insulating layer disposed directly over the source of the transistor 205 of Takahashi and with a via to allow the source electrode to be electrically connected to the source as suggested by Uchida because the insulating layer would provide some amount of separation between the source and the source line and it would have been a simple combination of elements of the two disclosures.
The combination of Takahashi and Uchida just described, however, does not teach “wherein the circuit layer comprises: a plurality of data lines electrically connected to the plurality of light emitting elements, and extending to the peripheral area”; and “at least a portion of the inorganic insulation pattern is located between the plurality of data lines and the plurality of readout lines.”
Ka, on the other hand, teaches a similar device (Ka Fig. 1) with data lines (Ka [0073]; Fig. 1, data lines 271), each disposed on the same layer as the source and drain electrodes of a transistor (Ka [0075-0076]; Fig. 4, driving TFT 20, driving source electrode 276, and driving drain electrode 277; note that the data line 271, driving source electrode 276, and driving drain electrode 277 are all disposed directly on top of the insulating interlayer 260) and between the transistor and a light sensor (Ka [0091]; Fig. 4, sensing TFT 30). Furthermore, Ka shows an insulation layer (Ka [0076]; Fig. 5, gate insulating layer 240) that is disposed within the circuit region (Ka [0076] and [0078]; Fig. 5, note that the gate insulating layer 240 extends between a semiconductor layer 232 and a gate electrode 255 on driving TFT 20) such that a portion of the layer would be disposed between a data line and a readout line when viewed from a top view (Ka [0056] and [0076]; Fig. 5, note that a portion of the gate insulating layer 240 is disposed between the output line 437 and the data line 271 when viewed from a top view).
The placement of the data line of Ka may be incorporated into the combined device of Takahashi and Uchida described in the discussion of claim 2 by placing the data line between the light-sensing element 60 and the light-receiving element 70 in said combined device. The combined device just described teaches “wherein the circuit layer comprises: a plurality of data lines electrically connected to the plurality of light emitting elements” (Takahashi [0105]; Fig. 4, note that the wirings 33 are connected to the pixel circuits 14; also see [0118]; Ka [0073]; Fig. 1, data lines 271), “and extending to the peripheral area” (Takahashi Fig. 4; note that the wirings 33 extend outside of the display area 11); and “at least a portion of the inorganic insulation pattern is located between the plurality of data lines and the plurality of readout lines” (Ka [0056] and [0076]; Fig. 5, note that a portion of the gate insulating layer 240 is disposed between the output line 437 and the data line 271 when viewed from a top view).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the placement of the data line of Ka into the combined device of Takahashi and Uchida described in the discussion of claim 2 because doing so would allow for an electrical connection between the data line and the corresponding light-emitting element and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818
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