DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on January 13, 2026.
Response to Amendment
Applicant's submission filed on January 13, 2026 has been entered. Claims 1-4 and 6-21 are pending in the current application. Claims 1-4 and 6-21 are rejected herein.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9 and 15 of U.S. Patent No. 11,968,843 in view of Kaczmarczyk et al. (Hereinafter Kaczmarczyk, U.S. Patent No. 5,625,796).
Regarding claim 1, U.S. Patent No. 11, 968,843 teaches:
A device, comprising:
a plurality of memory cells, the plurality of memory cells having a same type of magnetoresistive random access memory (MRAM) and including:
a first region of the plurality of memory cells; and
a second region of the plurality of memory cells;
a first addressing circuit positioned in close proximity to the first region of the plurality of memory cells and coupled to the first region of the plurality of memory cells via a first set of memory control lines, the first addressing circuit corresponding to the first region of the plurality of memory cells, the first addressing circuit is not coupled to the second region of the plurality of memory cells; and
a second addressing circuit positioned in close proximity to the second region of the plurality of memory cells and coupled to the second region of the plurality of memory cells via a second set of memory control lines, the second addressing circuit corresponding to the second region of the plurality of memory cells, the second addressing circuit different from the first addressing circuit, the second addressing circuit is not coupled to the first region of the plurality of memory cells (See claim 1 of U.S. Patent No. 11,968,843, as the teachings of claim1 of the instant application are present in the teachings of claim 1 of U.S. Patent No. 11,968,843 without patentable distinction. Note: Recitation of “the first addressing circuit is not coupled to the second region of the plurality of memory cells” and “the second addressing circuit is not coupled to the first region of the plurality of memory cells” in the amendments to the instant application does not provide patentable distinction over the limitations of claim 1 of U.S. Patent No. 11,968,843 that recite “a first addressing circuit … coupled to the first region of the plurality of memory cells via a first set of memory control lines, the first addressing circuit corresponding to the first region of the plurality of memory cells” and “a second addressing circuit … coupled to the second region of the plurality of memory cells via a second set of memory control lines, the second addressing circuit corresponding to the second region of the plurality of memory cells, the second addressing circuit different from the first addressing circuit”. Such limitations in the instant application do not provide patentable distinction as they are considered an obvious variation of the aforementioned limitations of claim 1 of U.S. Patent No. 11,968,843, that essentially teach different addressing circuits that are coupled to different corresponding memory regions via separate/different control lines (i.e. dedicated addressing circuits for separate memory regions), which would thus lead to an obvious variation of not coupling the separate memory regions to a non-corresponding addressing circuit.), and
U.S. Patent No. 11,968,843 does not explicitly disclose what Kaczmarczyk teaches:
the first addressing circuit and the second addressing circuit enabling simultaneous use of the first region and the second region of the plurality of memory cells (See Col. 3 line 1 – Col. 4 line 6 “Each memory access device can successfully communicate with each memory unit, regardless of operational time differences. In fact, due to the asynchronous operation of the memory access devices, each one of the memory units employed may be concurrently enabled and addressed by one of the available access devices, thereby optimizing system throughput by a more efficient management of system resources.” See claim 1 of Kaczmarczyk “wherein said memory interface device being connected to said first and second memory access devices and said first and second memory units via respective information buses, provides alternatively (a) concurrent data transfer to and from said first and second memory units and said first and second memory access devices, respectively, and (b) concurrent data transfer to and from said first and second memory units and said second and first memo access devices, respectively.” See Col. 5 lines 66 – Col. 6 line 2 ”memory addressing multiplexers 31 and 32 are responsible for assuring that the access requests of memory access devices 1,2,42 and 43 are presented to the appropriate memory units at the appropriate times.” See Claim 5 of Kaczmarczyk “memory addressing means, coupled to the plurality of memory units, for concurrently selecting different memory units from among the plurality of memory units; and”
See Claim 12 of Kaczmarczyk “first and second controller units, coupled to said first and second device interfaces, each controller unit being coupled to both said first and second multiplexers, for providing alternatively (a) concurrent communications between said first and second memory access devices and said first and second memories, respectively, and (b) concurrent communications between said first and second memory access devices and said second and first memories, respectively.” See Figure 4 of Kaczmarczyk. Memory addressing multiplexers enable concurrent/simultaneous use of first and second memories.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of U.S. Patent No. 11, 968,843 with the concurrent accessing of multiple memories method of Kaczmarczyk to optimize system throughput by a more efficient management of system resources.
Claims 10 and 17 of the instant application are rejected for the same reasons as claim 1 in view of claims 9 and 15 of U.S. Patent No. 11,968,843.
The teachings of claim 2 of the instant application are present in the teachings of claim 2 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 3 and 5 of the instant application are present in the teachings of claim 1 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 4 and 13 of the instant application are present in the teachings of claim 3 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claim 6 of the instant application are present in the teachings of claims 1 and 4 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 7 and 12 of the instant application are present in the teachings of claims 5 and 11 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claim 8 of the instant application are present in the teachings of claim 6 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 9 of the instant application are present in the teachings of claim 7 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 11 and 20 of the instant application are present in the teachings of claims 8 and 19 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claim 14 of the instant application are present in the teachings of claim 12 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claim 15 of the instant application are present in the teachings of claim 13 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claim 16 of the instant application are present in the teachings of claim 14 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 18 of the instant application are present in the teachings of claim 16 of U.S. Patent No. 11,968,843, without patentable distinction.
The teachings of claims 19 of the instant application are present in the teachings of claim 17 of U.S. Patent No. 11,968,843, without patentable distinction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 9-10, 13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hedden (U.S. Publication No. 2017/0287544) in view of Jung et al. (Hereinafter Jung, US Publication No. 2017/0220487) in view of Kaczmarczyk et al. (Hereinafter Kaczmarczyk, U.S. Patent No. 5,625,796).
Regarding claim 1, Hedden teaches:
A device, comprising:
a plurality of memory cells, the plurality of memory cells having a same type… (See [0011] “An example apparatus comprises a memory array including a main portion of memory cells and a redundant portion of memory cells.”) and including:
a first region of the plurality of memory cells (See [0011] “An example apparatus comprises a memory array including a main portion of memory cells…” The main portion/array of memory cells corresponds to the claimed first region.); and
a second region of the plurality of memory cells (See [0011] “An example apparatus comprises a memory array including a main portion of memory cells and a redundant portion of memory cells.” The redundant portion/array of memory cells corresponds to the claimed second region.);
a first addressing circuit positioned in close proximity to the first region of the plurality of memory cells (See [0025] “The main array 230 includes an address decode (e.g., row address decode) 246-1” See [0030] “The main portion 330 can be coupled to an address decode 346-1”) and coupled to the first region of the plurality of memory cells via a first set of memory control lines (See [0023] “The main memory array 230 can include a number of groups of memory cells 234-1, 234-2, 234-3, 234-4, 234-5, . . . , 234-M coupled to respective an access lines (e.g., the group of memory cells are “rows” of memory cells, as illustrated).” See [0029] “The main portion 330 can include a number of rows of cells 334-1, 334-2, 334-3, 334-4, 334-5, . . . , 334-M, where each row is coupled to an access line.” See [0030] “The main portion 330 can be coupled to an address decode 346-1, and the redundant portion 332 can be coupled to an address decode 346-2.” See Figure 2, Figure 3 and Figure 4, which teach an Address Decode Circuitry coupled to the Main Array via Control/Access lines.), the first addressing circuit corresponding to the first region of the plurality of memory cells (See [0025] “The main array 230 includes an address decode (e.g., row address decode) 246-1” See [0030] “The main portion 330 can be coupled to an address decode 346-1”), the first addressing circuit is not coupled to the second region of the plurality of memory cells (See Figure 2 in which the Address Decode circuit 246-1 is not directly coupled to the Redundant Array 232, as the Address Decode circuit 246-1 is a dedicated addressing circuit for the Main Array 230. The same teachings are provided in Figure 3. See [0025] and [0030].); and
a second addressing circuit positioned in close proximity to the second region of the plurality of memory cells (See [0025] “the redundant array 232 includes an address decode 246-2.”See [0030] “the redundant portion 332 can be coupled to an address decode 346-2.”) and coupled to the second region of the plurality of memory cells via a second set of memory control lines (See [0024] “The redundant array 232 can include a number of groups of memory cells 236-1, 236-2, 236-3, . . . , 236-N also coupled to respective access lines.” See [0030] “the redundant portion 332 can be coupled to an address decode 346-2.” See Figure 2, Figure 3 and Figure 4, which teach an Address Decode Circuitry coupled to the Redundant Array via Control/Access lines.), the second addressing circuit corresponding to the second region of the plurality of memory cells (See [0025] “the redundant array 232 includes an address decode 246-2.”See [0030] “the redundant portion 332 can be coupled to an address decode 346-2.”), the second addressing circuit different from the first addressing circuit (See [0025] “The main array 230 includes an address decode (e.g., row address decode) 246-1 and the redundant array 232 includes an address decode 246-2.” See [0030] “The main portion 330 can be coupled to an address decode 346-1, and the redundant portion 332 can be coupled to an address decode 346-2.”), the second addressing circuit is not coupled to the first region of the plurality of memory cells (See Figure 2 in which the Address Decode circuit 246-2 is not directly coupled to the Main Array 230, as the Address Decode circuit 246-2 is a dedicated addressing circuit for the Redundant Array 232. The same teachings are provided in Figure 3. See [0025] and [0030].),
Hedden does not explicitly disclose what Jung teaches:
a plurality of memory cells, the plurality of memory cells having a same type of magnetoresistive random access memory (MRAM) (See [0037] “As illustrated, the system-on-chip 100 includes a processor 110, a security interface (also referred to herein as security interface circuitry) 120, and a nonvolatile memory 130.” See [0050] where the nonvolatile memory 130 of figure 1 can be a MRAM. See Nonvolatile Memory MRAM 130 depicted in Figure 1, in which cache memory R1 and main memory R3 are part of the same Nonvolatile Memory MRAM 130, thus having the same MRAM type.).
While prior art Hedden does teach the plurality of memory cells to be several types of memory, such as DRAM, SRAM, STT RAM, PCRAM, TRAM, RRAM, NAND flash memory, and/or NOR flash memory (See [0020] of Hedden), Hedden does not explicitly disclose the plurality of memory cells to be magnetoresistive random access memory cells. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to perform simple substitution of the known memory types described in Hedden for the known magnetoresistive random access memory to obtain predictable results.
Hedden and Jung do not disclose what Kaczmarczyk teaches:
the first addressing circuit and the second addressing circuit enabling simultaneous use of the first region and the second region of the plurality of memory cells (See Col. 3 line 1 – Col. 4 line 6 “Each memory access device can successfully communicate with each memory unit, regardless of operational time differences. In fact, due to the asynchronous operation of the memory access devices, each one of the memory units employed may be concurrently enabled and addressed by one of the available access devices, thereby optimizing system throughput by a more efficient management of system resources.” See claim 1 of Kaczmarczyk “wherein said memory interface device being connected to said first and second memory access devices and said first and second memory units via respective information buses, provides alternatively (a) concurrent data transfer to and from said first and second memory units and said first and second memory access devices, respectively, and (b) concurrent data transfer to and from said first and second memory units and said second and first memo access devices, respectively.” See Col. 5 lines 66 – Col. 6 line 2 ”memory addressing multiplexers 31 and 32 are responsible for assuring that the access requests of memory access devices 1,2,42 and 43 are presented to the appropriate memory units at the appropriate times.” See Claim 5 of Kaczmarczyk “memory addressing means, coupled to the plurality of memory units, for concurrently selecting different memory units from among the plurality of memory units; and”
See Claim 12 of Kaczmarczyk “first and second controller units, coupled to said first and second device interfaces, each controller unit being coupled to both said first and second multiplexers, for providing alternatively (a) concurrent communications between said first and second memory access devices and said first and second memories, respectively, and (b) concurrent communications between said first and second memory access devices and said second and first memories, respectively.” See Figure 4 of Kaczmarczyk. Memory addressing multiplexers enable concurrent/simultaneous use of first and second memories.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the memory system of Hedden and the memory management system of Jung with the concurrent accessing of multiple memories method of Kaczmarczyk to optimize system throughput by a more efficient management of system resources.
Regarding claim 3, Jung teaches:
The device of claim 1, wherein the first region of the plurality of memory cells implements at least one cache memory; and wherein the second region of the plurality of memory cells implements at least one main memory (See [0039] “More specifically, the level manager LM of the processor 110 may manage an area of the nonvolatile memory 130 after dividing the area into at least three areas R1, R2, and R3. For example, the level manager LM may manage the at least three areas R1, R2, and R3 after distinguish the at least three areas R1, R2, and R3 into a cache memory area, a storage area, and a main memory area, respectively. For brevity of description, it will be assumed that the cache memory area is a first area R1, the storage area is a second area R2, and the main memory area is a third area R3.” See Claim 1 of Jung “A system-on-chip comprising: a magnetic random access memory including at least three memory areas,” See Claim 2 of Jung “The system-on-chip as set forth in claim 1, wherein the at least three memory areas comprise: a cache memory area requiring a highest input/output speed among the at least three memory areas; a main memory area;” See Figure 1, in which Nonvolatile Memory MRAM 130 implements a cache memory R1 and main memory R3.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the memory system of Hedden with the memory management system of Jung to improve data security by allowing the computing system to set different security levels for different parts of the memory (See [0007 of Jung.).
Regarding claim 4, Jung teaches:
The device of claim 3 wherein the plurality of memory cells include a third region of the plurality of memory cells that implements at least one secondary storage memory (See [0039] “For brevity of description, it will be assumed that the cache memory area is a first area R1, the storage area is a second area R2, and the main memory area is a third area R3.” The claimed secondary storage memory corresponds to the second storage area R2 of Nonvolatile Memory MRAM 130 depicted in Figure 1.).
Regarding claim 6, Hedden teaches:
The device of claim 1, comprising: an integrated circuit chip including the plurality of memory cells, the integrated circuit chip further including: at least one processing core integrated into the chip; a chip interface; and an on-chip bus system, which, in operation, communicatively couples together the at least one processing core, the plurality of memory cells and the chip interface (See [0019] “Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. For instance, the system 100 can be a hybrid memory cube (HMC) where control components (e.g., controller 140) can be located on a logic die and memory components (e.g., memory array 130 and redundant array 132) can be located in a number of stacked dies.” See [0021] “The memory device 120 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144.”).
Regarding claim 9, Jung teaches:
The device of claim 3 wherein the at least one cache memory and the at least one main memory have a same memory cell density (See Nonvolatile Memory MRAM 130 depicted in Figure 1, in which cache memory R1 and main memory R3 are part of the same Nonvolatile Memory MRAM 130, thus having the same MRAM cell density.).
While prior art Hedden does teach the plurality of memory cells to be several types of memory, such as DRAM, SRAM, STT RAM, PCRAM, TRAM, RRAM, NAND flash memory, and/or NOR flash memory (See [0020] of Hedden), Hedden does not explicitly disclose the plurality of memory cells to be magnetoresistive random access memory cells. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to perform simple substitution of the known memory types described in Hedden for the known magnetoresistive random access memory to obtain predictable results.
Regarding claim 10, Hedden teaches:
A system, comprising:
an integrated circuit chip, the integrated circuit chip having:
a processing core integrated into the chip;
memory circuitry integrated into the chip (See [0019] “Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. For instance, the system 100 can be a hybrid memory cube (HMC) where control components (e.g., controller 140) can be located on a logic die and memory components (e.g., memory array 130 and redundant array 132) can be located in a number of stacked dies.”), the memory circuitry including a plurality of memory cells organized into a plurality of regions of memory cells;
a first addressing circuit positioned in close proximity to a first region of the plurality of regions of memory cells and coupled to the first region via a first set of memory control lines,… the first addressing circuit corresponding to the first region; and
a second addressing circuit positioned in close proximity to a second region of the plurality of regions of memory cells and coupled to the second region via a second set of memory control lines,…the second addressing circuit corresponding to the second region, the second addressing circuit different from the first addressing circuit, the first addressing circuit is not coupled to the second region of the plurality of regions of memory cells, the second addressing circuit is not coupled to the first region of the plurality of regions of memory cells, and the first addressing circuit and the second addressing circuit enabling simultaneous use of the first region and the second region of the plurality of regions of memory cells (See rejection of claim 1.).
Hedden does not explicitly disclose what Jung teaches:
the plurality of memory cells each including magnetoresistive random access memory (MRAM) circuitry (See rejection of claim 1.);
the first region implementing at least one cache memory,
the second region implementing at least one main memory, (See [0039] “More specifically, the level manager LM of the processor 110 may manage an area of the nonvolatile memory 130 after dividing the area into at least three areas R1, R2, and R3. For example, the level manager LM may manage the at least three areas R1, R2, and R3 after distinguish the at least three areas R1, R2, and R3 into a cache memory area, a storage area, and a main memory area, respectively. For brevity of description, it will be assumed that the cache memory area is a first area R1, the storage area is a second area R2, and the main memory area is a third area R3.” See Claim 1 of Jung “A system-on-chip comprising: a magnetic random access memory including at least three memory areas,” See Claim 2 of Jung “The system-on-chip as set forth in claim 1, wherein the at least three memory areas comprise: a cache memory area requiring a highest input/output speed among the at least three memory areas; a main memory area;” See Figure 1, in which Nonvolatile Memory MRAM 130 implements a cache memory R1 and main memory R3.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the memory system of Hedden with the memory management system of Jung to improve data security by allowing the computing system to set different security levels for different parts of the memory (See [0007 of Jung.).
Regarding claim 13, Jung teaches:
The system of claim 10 wherein the plurality of regions of memory cells includes a third region of memory cells that implements a secondary storage memory (See rejection of claim 4. See [0039] “For brevity of description, it will be assumed that the cache memory area is a first area R1, the storage area is a second area R2, and the main memory area is a third area R3.”).
Regarding claim 15, Jung teaches:
The system of claim 10, comprising: a plurality of sets of memory control lines integrated into the chip, each set of memory control lines being coupled between the processing core and a respective memory cell of the plurality of memory cells (See [0106] “The nonvolatile memory cell array 131 is connected to the address decoder 132 through wordlines WL and connected to the read and write circuit 133 through bitlines BL. The nonvolatile memory cell array 131 includes a plurality of memory cells. Memory cells arranged in a column direction are connected to bitlines BL. For example, memory cell arranged in a column direction may be connected to bitlines BL and a plurality of cell groups may be connected to bitlines BL, respectively.” See [0114] “The data input/output circuit 134 is configured to transfer the externally transferred encrypted data DATA_E to the read and write circuit 133 through the data line DL.” See Figure 1 in view of Figure 10 and paragraphs [0106] and [0114], in which memory control lines are coupled between MRAM and the Level Manager (i.e. MMU).).
Regarding claim 15, Hedden teaches:
The system of claim 10, comprising: a plurality of sets of memory control lines integrated into the chip, each set of memory control lines being coupled between the processing core and a respective memory cell of the plurality of memory cells (See [0020] “The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines.” See [0023] “The main memory array 230 can include a number of groups of memory cells 234-1, 234-2, 234-3, 234-4, 234-5, . . . , 234-M coupled to respective an access lines (e.g., the group of memory cells are “rows” of memory cells, as illustrated).” See [0019] “Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. For instance, the system 100 can be a hybrid memory cube (HMC) where control components (e.g., controller 140) can be located on a logic die and memory components (e.g., memory array 130 and redundant array 132) can be located in a number of stacked dies.” See Figure 1 and Figure 2 in view of the cited paragraphs, in which control/access lines are coupled to the memory cells/array and are coupled between the memory cells/array and the host which may contain the processing core.).
Regarding claim 16, Hedden teaches:
The system of claim 10 wherein the plurality of memory cells has a uniform cell density (See [0020] “For instance, memory device 120 may include a number of arrays 130 (e.g., a number of banks of DRAM cells). Also, although arrays 130 and 132 are labeled as separate arrays, redundant array 132 can be a portion of array 130. For instance, array 130 can include a main portion and a redundant portion to which rows of the main portion may be remapped, for example.” See [0023] “The portion of the memory array illustrated in FIG. 2 can include a main memory array (e.g., non-redundant array) 230 and a redundant memory array 232.” See [0029] “The portion of the memory array illustrated in FIG. 3 can include a main portion 330 and a redundant portion 332 of a memory array.” The main array/portion and redundant array/portion depicted in Figure 1, Figure 2, Figure 3 and Figure 4 may be parts of the same memory array, thus having the same memory cell density.).
Regarding claim 16, Jung teaches:
The system of claim 10 wherein the plurality of memory cells has a uniform cell density (See Nonvolatile Memory MRAM 130 depicted in Figure 1, in which cache memory R1 and main memory R3 are part of the same Nonvolatile Memory MRAM 130, thus having the same MRAM cell density.).
Regarding claim 17, Hedden teaches:
A method of manufacturing an integrated circuit, comprising:
forming one or more processing cores of an integrated circuit chip in a substrate; and
forming one or more memory arrays of the integrated circuit chip in the substrate (See [0019] “Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 120 can be on the same integrated circuit. For instance, the system 100 can be a hybrid memory cube (HMC) where control components (e.g., controller 140) can be located on a logic die and memory components (e.g., memory array 130 and redundant array 132) can be located in a number of stacked dies.”);
forming a first addressing circuit positioned in close proximity to a first region of the one or more memory arrays and coupled to the first region of the one or more memory arrays via a first set of memory control lines,…the first addressing circuit corresponding to the first region of the one or more of memory arrays; and
forming a second addressing circuit positioned in close proximity to a second region of the one or more memory arrays and coupled to the second region of the one or more memory arrays via a second set of memory control lines,…the second addressing circuit corresponding to the second region of the one or more of memory arrays, and the second addressing circuit different from the first addressing circuit, the first addressing circuit is not coupled to the second region of the one or more memory arrays, the second addressing circuit is not coupled to the first region of the one or more memory arrays, and the first addressing circuit and the second addressing circuit enabling simultaneous use of the first region and the second region of the one or more arrays (See rejection of claim 1.).
Hedden does not explicitly disclose what Jung teaches:
the one or more memory arrays each including magnetoresistive random access memory (MRAM) circuitry (See rejection of claim 1.);
the first region of the one or more memory arrays implementing at least one cache memory,
the second region of the one or more memory arrays implementing at least one main memory, (See [0039] “More specifically, the level manager LM of the processor 110 may manage an area of the nonvolatile memory 130 after dividing the area into at least three areas R1, R2, and R3. For example, the level manager LM may manage the at least three areas R1, R2, and R3 after distinguish the at least three areas R1, R2, and R3 into a cache memory area, a storage area, and a main memory area, respectively. For brevity of description, it will be assumed that the cache memory area is a first area R1, the storage area is a second area R2, and the main memory area is a third area R3.” See Claim 1 of Jung “A system-on-chip comprising: a magnetic random access memory including at least three memory areas,” See Claim 2 of Jung “The system-on-chip as set forth in claim 1, wherein the at least three memory areas comprise: a cache memory area requiring a highest input/output speed among the at least three memory areas; a main memory area;” See Figure 1, in which Nonvolatile Memory MRAM 130 implements a cache memory R1 and main memory R3.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the memory system of Hedden with the memory management system of Jung to improve data security by allowing the computing system to set different security levels for different parts of the memory (See [0007 of Jung.).
Regarding claim 18, Jung teaches:
The method of claim 17 wherein the forming one or more memory arrays comprises simultaneously forming a plurality of memory arrays (See [0196] “Those skilled in the art will appreciate that the circuits, blocks, units and/or modules (e.g., determination circuits, cryptographic circuits, etc.) may be physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies.” See MRAM memory cell array 131, which is formed using semiconductor-based fabrication techniques or other manufacturing technologies) and wherein the plurality of memory arrays have a same memory cell density (See Nonvolatile Memory MRAM 130 depicted in Figure 1, in which cache memory R1 and main memory R3 are part of the same Nonvolatile Memory MRAM 130, thus having the same MRAM cell density.).
Regarding claim 19, Jung teaches:
The method of claim 17, comprising forming a plurality of sets of memory control lines of the chip on the substrate, a first set of the memory control lines coupling the one or more processing cores to memory cells of the at least one cache memory and a second set of the memory control lines coupling the one or more processing cores to memory cells of the at least one main memory (See [0106] “The nonvolatile memory cell array 131 is connected to the address decoder 132 through wordlines WL and connected to the read and write circuit 133 through bitlines BL. The nonvolatile memory cell array 131 includes a plurality of memory cells. Memory cells arranged in a column direction are connected to bitlines BL. For example, memory cell arranged in a column direction may be connected to bitlines BL and a plurality of cell groups may be connected to bitlines BL, respectively.” See [0114] “The data input/output circuit 134 is configured to transfer the externally transferred encrypted data DATA_E to the read and write circuit 133 through the data line DL.” See Figure 1 in view of Figure 10 and paragraphs [0106] and [0114], in which memory control lines are coupled between MRAM and the Level Manager (i.e. MMU). The control lines connect the MRAM memory/cells (which include the cache and main memory) to the processor core).
Claims 2, 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hedden in view of Jung in view of Kaczmarczyk in view of Oh et al. (Hereinafter Oh, US Publication No. 2013/0044538).
Regarding claim 2, Jung teaches:
The device of claim 1, comprising: at least one memory management circuit (MMU) integrated into the chip (See [0038] “The processor 110 may include or drive a level manager LM to manage areas of the nonvolatile memory 130 according to functions. For example, the level manager LM may be a hardware circuit or software stored in a programmable read only memory (PROM).”),
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the memory system of Hedden with the memory management system of Jung to improve data security by allowing the computing system to set different security levels for different parts of the memory (See [0007 of Jung.).
Jung does not explicitly disclose what Oh teaches:
wherein at least a portion of the at least one MMU is positioned on at least a portion of the plurality of memory cells (See [0006] and Abstract in view of Figures 2, 9, 10 and 14, which teach a stacked MRAM device. Under broadest reasonable interpretation, portions of circuitry provided in the system necessary for memory management will be positioned on at least a portion of the MRAM circuit in a stacked memory device environment.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply a known technique of stacking memory (i.e. MRAM devices) to a known memory device, such as MRAM devices described in the system of Jung, ready for improvement to yield predictable results. Specifically, stacking memory/MRAM devices would increase memory density and performance while reducing chip size/footprint.
Regarding claim 11, Oh teaches:
The system of claim 10, wherein the first addressing circuit is stacked on the first region of the plurality of regions of memory cells, and the second addressing circuit is stacked on the second region of the plurality of regions of memory cells (See rejection of claim 2. See [0006] and Abstract in view of Figures 2, 9, 10 and 14, which teach a stacked MRAM device including addressed lines/circuitry on the MRAM circuit. Under broadest reasonable interpretation, the circuitry provided in the system necessary for memory management is positioned on the MRAM circuit in a stacked memory device environment.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to apply a known technique of stacking memory (i.e. MRAM devices) to a known memory device, such as MRAM devices described in the system of Jung, ready for improvement to yield predictable results. Specifically, stacking memory/MRAM devices would increase memory density and performance while reducing chip size/footprint.
Regarding claim 20, Oh teaches:
The method of claim 17, wherein the first addressing circuit is formed to be stacked on the first region of the one or more memory arrays, and the second addressing circuit is formed to be stacked on the second region of the one or more memory arrays (See rejection of claim 2. See [0006] and Abstract in view of Figures 2, 9, 10 and 14, which teach a stacked MRAM device including addressed lines/circuitry on the MRAM circuit. Under broadest reasonable interpretation, the circuitry provided in the system necessary for memory management is positioned on the MRAM circuit in a stacked memory device environment.).
Claims 7-8, 12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hedden in view of Jung in view of Kaczmarczyk in view of Takeda et al. (Hereinafter Takeda, US Publication No. 2014/0297920).
Regarding claim 7, Takeda teaches:
The device of claim 3 wherein the at least one cache memory includes a level-1 cache, a level-2 cache and a level-3 cache (See Figure 19, which depicts an MRAM level-1 cache, an MRAM level-2 cache and an MRAM level-3 cache).
Although prior art Jung teaches MRAM cache memory, Jung does not teach the MRAM cache memory to include a level-1 cache, a level-2 cache and a level-3 cache. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to provide multiple cache levels (as taught in Takeda) to the caching method of Jung to improve cache performance by adding multiple cache layers, thus increasing speed of data access and allowing more data to be stored closer to the processing core.
Regarding claim 8, Takeda teaches:
The device of claim 3 wherein the at least one cache memory includes an instruction cache and a data cache (See Figure 19, which depicts an MRAM level-1 instruction cache and an MRAM level-1 data cache).
Regarding claim 12, Takeda teaches:
The system of claim 10 wherein the at least one cache memory includes a level-1 cache, a level-2 cache and a level-3 cache (See Figure 19, which depicts an MRAM level-1 cache, an MRAM level-2 cache and an MRAM level-3 cache).
Although prior art Jung teaches MRAM cache memory, Jung does not teach the MRAM cache memory to include a level-1 cache, a level-2 cache and a level-3 cache. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to provide multiple cache levels (as taught in Takeda) to the caching method of Jung to improve cache performance by adding multiple cache layers, thus increasing speed of data access and allowing more data to be stored closer to the processing core.
Regarding claim 21, Takeda teaches:
The method of claim 19, wherein the at least one cache memory includes a level-1 cache, a level-2 cache and a level-3 cache (See rejection of claim 7 and claim 12.).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hedden in view of Jung in view of Kaczmarczyk in view of Chen et al. (Hereinafter Chen, US Patent No. 7,023,726).
Regarding claim 14, Chen teaches:
The system of claim 10 wherein the plurality of memory cells comprises at least two types of magnetoresistive random access memory (MRAM) memory cells (See Col. 3, lines 38-33 “The hybrid MRAM architecture 2 comprises a plurality of MRAM arrays constituted by a plurality of 1T1MTJ architecture MRAM cells, such as two 1T1MTJ MRAM arrays 211, 212, and by a plurality of XPC architecture MRAM cells, such as two XPC MRAM arrays 221, 222.” See Col. 4, lines 1-10 “FIG. 3 is a diagram schematically illustrating a hybrid MRAM architecture according to a preferred embodiment of the present invention for being adapted to an MCU, in which the MCU 3 comprises a controller unit 31, a level 1 cache 32 constituted by a plurality of MRAM arrays having 1T1MTJ architecture MRAM cells respectively; a level 2 cache 33 constituted by a plurality of MRAM arrays having 1T1MTJ architecture MRAM cells respectively; a level 3 storage memory 34 constituted by a plurality of MRAM arrays having XPC architecture MRAM cells respectively;” Figure 2 depicts two types of MRAM cells, in which one type is that of 1T1MTJ architecture MRAM cells and the other type is that of XPC architecture MRAM cells. In Figure 3, a level 1 cache and level 2 cache are comprised of 1T1MTJ architecture MRAM cells while level 3 storage memory is comprised of XPC architecture MRAM cells).
Although prior art Jung teaches MRAM circuitry, Jung does not explicitly teach the MRAM circuitry to comprise at least two types of MRAM cells. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to provide multiple types of MRAM memory technology/cells, as taught in the hybrid MRAM architecture of Chen, to the MRAM devices of Jung to realize the benefits of multiple types of MRAM technology by using different MRAM technology in different memory applications to increase the operational efficiency of the system. For example, such benefits/motivation is evident in Col. 4 line 61-Col. 5 line 6 of Chen: “It is inferable from the above description that the hybrid MRAM architecture according to the present invention is capable of having two MRAMs of different characteristics (the 1T1MTJ architecture and the XPC architecture) integrated so as to use the MRAM architecture appropriate in different memory applications as needed in practice to increase the operational efficiency of the whole system. For example, the 1T1MTJ architecture MRAM having fast access speed feature serves as the cache in the memory portion where faster access is required, and the XPC architecture MRAM having high storage density feature serves as the storage memory in the memory portion where higher storage density is required.”
Response to Arguments
Applicant's arguments filed January 13, 2026 have been fully considered but are not persuasive. On page 9 of applicant’s arguments, applicant’s representative submitted that even if Kaczmarczyk is combined with Hedden and Jung, they still do not teach or suggest "the second addressing circuit different from the first addressing circuit and the first addressing circuit and the second addressing circuit enabling simultaneous use of the first region and the second region of the plurality of memory cells," as recited in claim 1. After citing FIG. 3 and col. 3, line 45- col. 4, line 3 of Kaczmarczyk, applicant’s representative submitted that Hedden's address decode 346-1 and the address decode 346-2 will not simultaneously use the main array 330 and the redundant array 332, respectively, because such a simultaneous use is against the fundamental principle of dividing the memory into main array and redundant array. Examiner respectfully disagrees and maintains that the combination of Kaczmarczyk with Hedden and Jung is proper to arrive at the argued limitation, as previously submitted in examiner’s response to arguments and examiners motivation and obviousness rationale.
On page 9 of applicant’s arguments, applicant submitted that there is no suggestion or motivation to combine Hedden and Kaczmarczyk because the basic principles of the Kaczmarczyk and the Hedden system do not work together. Applicant’s representative submitted that in Hedden, address decode 346-1 is coupled to the main array 330 only and the address decode 346-2 is coupled to the redundant array 332 only, and only one of the main array or the redundant array is used for accessing a physical address in Hedden. Applicant’s representative further submitted that Kaczmarczyk used the interface to enable each memory access device to access each of the memory units, which is fundamentally different from the main array and redundant array scheme of Hedden and cannot be combined with the contents of Hedden cited by the Office in the rejections. Examiner respectfully disagrees that Hedden, Jung, and Kaczmarczyk cannot be combined due to the alleged differences between them. Examiner maintains that Hedden and Kaczmarczyk can be combined and provides that such combination is proper, as both prior art references are analogous art, and the portion relied upon in Kaczmarczyk (i.e. concurrent memory access of multiple memory units) is an obvious combination to one of ordinary skilled in the art for the reasons set forth in the rejections of claim 1. That is, examiner isn’t relying on the combination of the entire system of Kaczmarczyk, but merely the portion identified as being obvious to one of ordinary skilled in the art. Therefore, such combination is proper.
On page 10 of applicant’s arguments, applicant submitted that Kaczmarczyk does not teach or suggest concurrent memory access, and that Kaczmarczyk only discusses “[e]ach memory access device can successfully communicate with each memory unit, regardless of operational time difference”. Examiner disagrees, as the concurrent memory access of Kaczmarczyk is taught in Col. 3 line 1 – Col. 4 line 6, claim 1 of Kaczmarczyk, Col. 5 lines 66 – Col. 6 line 2, Claim 5 of Kaczmarczyk, Claim 12 of Kaczmarczyk, and Figure 4 of Kaczmarczyk. For example, see Figure 4 of Kaczmarczyk. Memory addressing multiplexers enable concurrent/simultaneous use of first and second memories. See Col. 3 line 1 – Col. 4 line 6 “due to the asynchronous operation of the memory access devices, each one of the memory units employed may be concurrently enabled and addressed by one of the available access devices, thereby optimizing system throughput by a more efficient management of system resources.” See claim 1 of Kaczmarczyk “provides alternatively (a) concurrent data transfer to and from said first and second memory units and said first and second memory access devices, respectively, and (b) concurrent data transfer to and from said first and second memory units and said second and first memo access devices, respectively.” See Col. 5 lines 66 – Col. 6 line 2 ”memory addressing multiplexers 31 and 32 are responsible for assuring that the access requests of memory access devices 1,2,42 and 43 are presented to the appropriate memory units at the appropriate times.” See Claim 5 of Kaczmarczyk “memory addressing means, coupled to the plurality of memory units, for concurrently selecting different memory units from among the plurality of memory units;” On page 10 of applicant’s arguments, applicant submitted that one of ordinary skill in the art, even with access to Hedden and Kaczmarczyk, will not obtain the noted features of claim 1 without hindsight teaching of the claim 1 features of the present application. Examiner respectfully disagrees and submits that one of ordinary skill in the art would be able to obtain the argued features of claim 1 without hindsight due to the analogous nature of the prior art (i.e. Hedden and Kaczmarczyk) as well as the explicit teachings of the prior art cited by examiner. For the reasons provided, applicant’s arguments are not persuasive, and all pending claims in the instant application are rejected herein.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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