Prosecution Insights
Last updated: October 04, 2026
Application No. 18/627,457

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Apr 05, 2024
Priority
Apr 13, 2023 — JP 2023-065679
Examiner
YI, CHANGHYUN
Art Unit
Tech Center
Assignee
Japan Display Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1026 granted / 1092 resolved
+34.0% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
40 currently pending
Career history
1135
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
34.8%
-5.2% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1092 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant's election of Group I (claims 1–7) in the response filed on 7/9/26, is acknowledged. Applicant did not expressly traverse the restriction requirement and did not distinctly and specifically identify any alleged error in the restriction requirement or provide reasons why the restriction requirement was improper. Accordingly, the election is treated as an election without traverse. See MPEP § 818.01(a). Claims 1–7, corresponding to elected Group I, are therefore examined on the merits in the present Office action. Claims 8–11 remain withdrawn from consideration as being directed to nonelected subject matter. Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01). This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc. The following title is suggested: “Display Apparatus Including an Inorganic Light-Emitting Diode Mounted on a Diode-Containing Substrate Structure and Method of Manufacturing the Same” Because the present title, “Display Apparatus and Method of Manufacturing the Same,” is overly broad because it identifies only the general field of the invention. The claimed subject matter is more specifically directed to an inorganic light-emitting diode mounted on a substrate structure that includes another diode element. A more descriptive title would therefore better identify the nature of the invention. Specification The specification is objected to because of the following informalities: On page 19, line 7, the term “burrier” in the phrase “a shape of a tunnel burrier is unsymmetric” appears to be a typographical error. The term “burrier” should be corrected to “barrier.” Appropriate correction is required. Additionally, on page 20, line 5, the term “ta” in the phrase “does not show ta contact portion” appears to be a typographical error. Appropriate correction is required. Claim Objections Claim 1 is objected to because of the following informality: The phrase “the second diode element includes” following the recitation of the second bump electrode is grammatically improper. Specifically, claim 1 first recites that “the substrate structure includes” a series of components, ending with the second bump electrode, and then immediately recites “the second diode element includes” without a transitional term separating the two clauses. The transitional term “wherein” is needed before “the second diode element includes” to make clear that the subsequent recitation is a further limitation defining the previously recited second diode element, rather than a continuation of the preceding recitation concerning the second bump electrode. Appropriate correction is required. For example, the claim may be amended to recite “wherein the second diode element includes:”. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 3-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 20220320055). Regarding claim 1, Fig. 3 of Choi discloses a display apparatus comprising: a first diode element 300 (sub-LED 300) including a first anode electrode 309 (second p-type electrode 309) and a first cathode electrode 301 (second n-type electrode 301), and being an inorganic light-emitting diode element [0116]. In particular, Choi discloses that second-first semiconductor layer 303 of sub-LED 300 comprises a semiconductor material of a p-type gallium nitride (p-GaN) group and second-second semiconductor layer 307 comprises a semiconductor material of an n-type gallium nitride (n-GaN) group. Choi further discloses that second p-type electrode 309 is disposed on the p-type semiconductor layer 303 and second n-type electrode 301 is disposed on the n-type semiconductor layer 307 [0116]. Thus, Choi expressly discloses the respective semiconductor polarities associated with electrodes 309 and 301. With respect to the recited first anode electrode and first cathode electrode, although Choi refers to electrodes 309 and 301 as a “second p-type electrode” and a “second n-type electrode,” respectively, rather than expressly labeling electrodes 309 and 301 as an “anode” and a “cathode,” Choi expressly discloses the respective semiconductor polarities associated with these electrodes. Specifically, electrode 309 is disposed on p-type GaN semiconductor layer 303, whereas electrode 301 is disposed on n-type GaN semiconductor layer 307. Thus, the disclosed structure and polarity of sub-LED 300 establish electrode 309 as the anode-side electrode and electrode 301 as the cathode-side electrode of the inorganic light-emitting diode. Choi further discloses a substrate structure 106b/106c on which the first diode element 300 is mounted, as shown in Fig. 3; wherein the substrate structure includes: a first terminal 112 (second connecting electrode 112) connected to the first anode electrode 309. Specifically, Choi discloses that second p-type electrode 309 of sub-LED 300 is electrically connected to second connecting electrode 112 [0117]; a second terminal 111 (first connecting electrode 111) connected to the first cathode electrode 301. Specifically, Choi discloses that second n-type electrode 301 of sub-LED 300 is electrically connected to first connecting electrode 111 [0117]; a second diode element 120 (LED 120) electrically connected to each of the first terminal 112 and the second terminal 111. Choi discloses that LED 120 includes first n-type electrode 121, an emitting layer, and first p-type electrode 129 [0069]. Choi further discloses that first p-type electrode 129 is electrically connected to second connecting electrode 112 and first n-type electrode 121 is electrically connected to first connecting electrode 111; a first bump electrode 115b formed on the first terminal 112 and electrically connected to each of the first terminal 112 and the first anode electrode 309; and a second bump electrode 115a formed on the second terminal 111 and electrically connected to each of the second terminal 111 and the first cathode electrode 301. With respect to the bump electrodes, Choi expressly discloses in [0104] that first bump 115a is disposed between first connecting electrode 111 and the n-type electrode of the sub-LED and that second bump 115b is disposed between second connecting electrode 112 and the p-type electrode of the sub-LED for providing stable electrical connections therebetween. In the Fig. 3 configuration, the corresponding n-type and p-type electrodes of sub-LED 300 are electrodes 301 and 309, respectively, as expressly disclosed in [0116]. Thus, the bump arrangement shown in Fig. 3 provides the electrical connections: 309 → 115b → 112, and 301 → 115a → 111. Choi further discloses that the second diode element 120 includes a second cathode electrode 129 (first p-type electrode 129) connected to the first terminal 112, and a second anode electrode 121 (first n-type electrode 121) connected to the second terminal 111. In particular, Choi identifies first p-type electrode 129 of LED 120 as the cathode and first n-type electrode 121 as the anode. Further, [0117] expressly discloses that second p-type electrode 309 of sub-LED 300 is electrically connected to second connecting electrode 112, which is connected to first p-type electrode 129 of LED 120, and that second n-type electrode 301 of sub-LED 300 is electrically connected to first connecting electrode 111, which is connected to first n-type electrode 121 of LED 120. Accordingly, Choi discloses the claimed electrical relationships as follows: first anode electrode 309 → first bump electrode 115b → first terminal 112 → second cathode electrode 129, and first cathode electrode 301 → second bump electrode 115a → second terminal 111 → second anode electrode 121. Regarding claim 3, Choi discloses the display apparatus of claim 1 as discussed above. Choi further discloses that the substrate structure includes a plurality of wiring layers including a first wiring layer and a plurality of insulating layers including a first insulating layer 106b. As shown in Fig. 3, Choi discloses a multilayer substrate structure including interlayer insulating layers 106b and 106c, and conductive wiring, electrode, and pad structures formed at different levels of the multilayer substrate structure (Fig. 3 and [0065]). Choi further discloses that the first terminal 112 and the second terminal 111 are formed in the first wiring layer arranged on the first insulating layer 106b. As shown in Fig. 3, connecting electrodes 112 and 111, corresponding respectively to the claimed first and second terminals as mapped above with respect to claim 1, are formed at a wiring level arranged on first insulating layer 106b and provide electrical connection to underlying conductive structures 108 and 109b through the respective contact structures. Choi further discloses that the second diode element 120 is formed in a wiring layer different from the first wiring layer. As shown in Fig. 3, LED 120, corresponding to the claimed second diode element, is formed at a different wiring level associated with interlayer insulating layer 106c, whereas terminals 112 and 111 are formed at the first wiring level associated with insulating layer 106b. The different wiring levels are electrically interconnected through the respective first and second electrode contact holes 114a and 114b. Thus, Choi discloses terminals 112 and 111 formed in a first wiring layer arranged on first insulating layer 106b, and second diode element 120 formed in a wiring layer different from the first wiring layer, as required by claim 3. Regarding claim 4, Choi discloses the display apparatus of claim 3 as discussed above. Choi further discloses that the second diode element 120 is formed at a position overlapping the first diode element 300 in a thickness direction of the substrate structure. Specifically, as shown in Fig. 3, sub-LED 300, corresponding to the claimed first diode element, is disposed vertically over LED 120, corresponding to the claimed second diode element. Choi expressly states in [0117] that “the sub LED 300 is disposed over a deteriorated LED 120.” Thus, Fig. 3 and [0117] disclose that LED 120 and sub-LED 300 are positioned at different vertical levels and overlap one another in the thickness direction of the substrate structure, as required by claim 4. Regarding claim 5, Choi discloses the display apparatus of claim 1 as discussed above. Choi further discloses that the first terminal 112 and the second terminal 111 are arranged on a first insulating layer 106b, and the second diode element 120 is formed on the first insulating layer 106b, as shown in Fig. 3. Specifically, Fig. 3 discloses a multilayer insulating structure in which third interlayer insulating layer 106c is formed on a top surface of second interlayer insulating layer 106b, and LED 120, corresponding to the claimed second diode element, is formed within the third interlayer insulating layer 106c over the second interlayer insulating layer 106b. Connecting electrodes 112 and 111, corresponding respectively to the claimed first and second terminals as mapped above, are likewise arranged over/on the second interlayer insulating layer 106b and provide electrical connections to LED 120 through the respective contact structures. Thus, second interlayer insulating layer 106b corresponds to the claimed first insulating layer. Fig. 3 discloses terminals 112 and 111 arranged on first insulating layer 106b and second diode element 120 formed on first insulating layer 106b, with LED 120 being formed within insulating layer 106c disposed on the top surface of insulating layer 106b. Regarding claim 7, Choi discloses the display apparatus of claim 1 as discussed above. Choi further discloses that the second diode element 120 includes a semiconductor layer (Fig. 3; [0131]). Specifically, Choi discloses that LED 120, corresponding to the claimed second diode element, includes a first-first semiconductor layer 123 comprising a semiconductor material of an n-type gallium nitride (n-GaN) group, and a first-second semiconductor layer 127 comprising a semiconductor material of a p-type gallium nitride (p-GaN) group [0131]. Thus, Choi expressly discloses that second diode element 120 includes semiconductor layers 123 and 127, thereby satisfying the additional limitation of claim 7. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220320055) in view of in view of Sakong et al. (US 20190305202). Regarding claim 2, Choi discloses the display apparatus of claim 1 as discussed above, including first and second bump electrodes for electrically connecting the respective terminals to the electrodes of the inorganic light-emitting diode. But Choi does not expressly disclose that each of the first bump electrode and the second bump electrode is made of a stacking film of a plurality of metal films. However, Sakong teaches this feature. In particular, Sakong discloses first and second bumps 111 and 112 (Fig. 7 and [0043]). Sakong further teaches that the first bump 111 includes a plurality of stacked metal layers 111a and 111b, and that the second bump 112 includes a plurality of stacked metal layers 112a and 112b ([0077] and [0079]). Thus, Sakong teaches first and second bump electrodes, each made of a stacking film of a plurality of metal films, as required by claim 2. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second bump electrodes of Choi to have the stacked multilayer metal structure taught by Sakong, because multilayer metal bump structures were known for providing the respective electrical, interfacial, and bonding functions of the constituent metal layers and thereby providing a reliable electrical and mechanical connection between the light-emitting diode electrodes and the corresponding connecting electrodes. Such a modification would have amounted to the use of a known multilayer bump structure for its known purpose and would have yielded the predictable result of providing first and second bump electrodes having a plurality of stacked metal films. Accordingly, it would have been obvious to modify Choi in view of Sakong to provide each of the first bump electrode and the second bump electrode as a stacking film of a plurality of metal films, as required by claim 2. Therefore, claim 2 is unpatentable over Choi in view of Sakong. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220320055) in view of Zhang et al. (US 20230038312). Regarding claim 6, Choi discloses the display apparatus of claim 1 as discussed above, including second diode element 120 electrically connected to the first and second terminals 112 and 111. But Choi does not expressly disclose that the second diode element is made of a stacking film, the stacking film including a first metal layer being the second cathode electrode, a metal oxide layer covering the first metal layer, and a second metal layer being the second anode electrode and covering the first metal layer through the metal oxide layer. However, Zhang teaches the additional stacked diode structure. In particular, Zhang discloses an LED having a non-inverted stacked architecture, as shown in Fig. 4 [0035]. Fig. 4 shows the constituent layers of the LED vertically stacked with cathode 7 at a lower portion of the stack, composite film 6 including aluminum oxide film 61 above cathode 7, and anode 1 at an upper portion of the stack. More particularly, Zhang discloses that the LED includes anode 1 and cathode 7 arranged opposite to each other, a luminescent layer 4 arranged between anode 1 and cathode 7, an electron transport layer 5 arranged between cathode 7 and luminescent layer 4, and composite film 6 arranged between cathode 7 and electron transport layer 5. Zhang further discloses that composite film 6 includes aluminum oxide film 61, which is a metal oxide film [0043]. Accordingly, Zhang teaches the claimed stacking relationship, including: a first metal layer being the second cathode electrode — cathode 7; a metal oxide layer covering the first metal layer — aluminum oxide film 61, which is arranged over cathode 7; and a second metal layer being the second anode electrode and covering the first metal layer through the metal oxide layer — anode 1, which is arranged over cathode 7 through the vertically intervening layers including aluminum oxide film 61. Thus, Zhang Fig. 4 teaches the claimed stacking order in which aluminum oxide film 61 covers cathode 7 and anode 1 covers cathode 7 through aluminum oxide film 61, thereby providing the stacking arrangement required by claim 6. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the stacked LED structure taught by Zhang as the second diode element 120 of Choi, because Zhang teaches a known vertically stacked LED architecture having an anode and a cathode arranged opposite to each other and an intervening metal-oxide-containing layer. Employing Zhang's known stacked LED architecture for Choi's second diode element would have been the use of a known LED structure for its known light-emitting function, and would have predictably resulted in Choi's second diode element having the claimed vertically stacked electrode and metal-oxide arrangement. Accordingly, it would have been obvious to modify Choi in view of Zhang such that the second diode element includes the claimed stacking film having the first metal layer being the second cathode electrode, the metal oxide layer covering the first metal layer, and the second metal layer being the second anode electrode and covering the first metal layer through the metal oxide layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Apr 05, 2024
Application Filed
Aug 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.1%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1092 resolved cases by this examiner. Grant probability derived from career allowance rate.

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