DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) filed on April 5th, 2024 and January 7th, 2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US PGPub 2023/0010657 (hereinafter referred to as “Wu”) in view of Chou et al., US PGPub 2016/0322462 A1 (hereinafter referred to as “Chou”).
Regarding Claim 1, Wu discloses a method (FIG. 3A, method 100; [0030]), comprising:
forming a fin structure from a substrate (FIG. 6, operation 106, fin structures 29; [0037]);
depositing an insulating material around the fin structure ([0038]);
recessing the insulating material (FIG. 7, operation 108, isolation insulating layer 15; [0041]);
forming a sacrificial gate structure over a first portion of the fin structure (FIG. 8, operation 110, sacrificial gate structure 49; [0042]),
wherein a first portion of the insulating material is covered by the sacrificial gate structure (as indicated by the red arrow annotation in FIG. 8 below), and a second portion of the insulating material is exposed (as indicated by the teal arrow annotation in FIG. 8 below);
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depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure (FIG. 9, operation 112, cover layer 40; [0045]);
and recessing the second portion of the fin structure (FIG. 11A, operation 114, forming S/D trench 27; [0048]).
Wu is silent regarding modifying a top surface of the exposed second portion of the insulating material, wherein the modified top surface has a profile different from a top surface of the first portion of the insulating material.
However, Chou, which is directed to a similar manufacture of FinFET and Gate-All-Around structures teaches that one can use a combination of tilt ion implantation and etching to modify the surface of isolation regions, even after the formation of the sacrificial dummy gate (wherein the requisite formation steps cause damage or unwanted etching of the exposed isolation regions), to control the topography of the isolation region surface from concave to convex to flat (Chou FIGs. 7C-7D, 8A-8C, isolation regions 316a, 316b; [0050-0055, 0058-0061, 0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu with the teachings of Chou of modifying a top surface of the exposed second portion of the insulating material, wherein the modified top surface has a profile different from a top surface of the first portion of the insulating material for the benefit of control of the isolation region surface shape from concave to convex to flat, allowing for control of “active region and/or epitaxial growth shapes that improve performance of the FinFET structure” [0061].
Further, in such a combined method, the teachings of Wu to deposit a first spacer on the sacrificial gate structure and a second portion of the fin structure would then be done after the modifying of the top surface, such that Wu in view of Chou discloses, as discussed above, after the modifying of the top surface, depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure (Wu FIG. 9, operation 112, cover layer 40; [0045]).
Regarding Claim 2, Wu in view of Chou (Wu/Chou) discloses the method of claim 1 as discussed above.
Wu further discloses further comprising depositing a second spacer on the first spacer (FIG. 9, additional cover layer 47; [0046]).
Regarding Claim 3, Wu/Chou discloses the method of claim 2, as discussed above.
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Wu further discloses further comprising removing horizontal portions of the first and second spacers prior to recessing the second portion of the fin structure (FIG. 10A to FIG. 11A, see figures below showing horizontal portions of cover layer 40, and thus additional cover layer 47 (not shown in figure), in FIG. 10A and [0047], as indicated by the red dashed box annotations, which are then etched (removed) in FIG. 11A, operation 114 (note red dashed box annotations in S/D trench 27 indicating horizontal portions of cover layer 40 has been removed).
As the horizontal portions are directly on top of the semiconductor layers 20 and 25 to be etched (i.e., exposed fin structure 29), the spacers must necessarily be etched (removed) prior to recessing the exposed fin structure 29).
Regarding Claim 5, Wu/Chou discloses the method of claim 1, as discussed above.
Wu further discloses wherein a well portion is exposed after the recessing of the second portion of the fin structure (FIG. 11A, S/D trench 27, wherein substrate 10 (or the bottom part of the fin structures 29, i.e., a well portion) “is also partially etched” [0048]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chou (Wu/Chou) as applied to claim 1 above, and further in view of Fu et al., US PGPub 2016/0300931 A1 (hereinafter referred to as “Fu”).
Regarding Claim 4, Wu/Chou discloses the method of claim 1 as discussed above.
Neither Wu nor Chou explicitly disclose wherein the second portion of the insulating material is recessed during the recessing of the second portion of the fin structure.
However, Fu, which is similarly directed to fabrication of FinFETs using insulating material (shallow trench insulation or STI) to isolate fin structures, teaches the simultaneous recessing of the STI oxide and fin structure (FIGs. 2A-2C, Si lines 202, STI oxide 210; [0015]) for the benefit of “a reliable and well-formed Fin-FET structure” wherein you do not need additional recess or epitaxial growth steps, helping to “improved fabrication” and thus manufacturing efficiency (Fu [0015]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu/Chou with the simultaneous recessing of the insulating material and fin structure as taught by Fu such that wherein the second portion of the insulating material is recessed during the recessing of the second portion of the fin structure for the benefit of “improved fabrication” and manufacturing efficiency to fabricate “a reliable and well-formed Fin-FET structure” without need for additional recessing or epitaxial growth steps (such as “adding spacers during the [epitaxial regrowth steps] CRF steps”) (Fu [0015]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Chou as applied to claim 1 above, and further in view of Shih et al., US PGPub 2021/0366914 A1 (hereinafter referred to as “Shih”).
Regarding Claim 6, Wu/Chou disclose the method of claim 5, as discussed above.
Neither Wu nor Chou explicitly disclose further comprising: depositing a first semiconductor material on the well portion;
depositing a second semiconductor material over the first semiconducting material;
and depositing a third semiconductor material on the second semiconductor material.
However, Shih, which is directed to a similar method of manufacturing FinFETs, teaches that growing multiple layers of semiconducting material in the well portion on the fins is beneficial to “prevent adjacent epitaxy layers…from contacting or even merging with other” (FIGs. 16A-16D, epitaxy layers 312A, 314A in recesses R1 and on semiconductor fins 228, 224, [0040]; FIGs. 17A-17D, epitaxy layers 312B, 314B over epitaxy layers 312A, 314A, [0041]; FIGs. 18A-18E, epitaxy layers 312C, 314C over epitaxy layers 312B, 314B, [0042]; [0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu/Chou with the multiple semiconducting material layer teachings of Shih, such the method is further comprising:
depositing a first semiconductor material on the well portion (FIGs. 16A-16D, epitaxy layers 312A, 314A in recesses R1 and on semiconductor fins 228, 224, [0040);
depositing a second semiconductor material over the first semiconductor material (FIGs. 17A-17D, epitaxy layers 312B, 314B over epitaxy layers 312A, 314A, [0041]);
and depositing a third semiconductor material on the second semiconductor material (FIGs. 18A-18E, epitaxy layers 312C, 314C over epitaxy layers 312B, 314B, [0042]; [0053]) for the benefit of preventing unwanted “contacting or merging” of different growth layers (e.g., such as opposing p- or n-type sections of the overall structure, wherein the relevant source/drain trenches, i.e., well portions of the second portion of the fin structures, could contact or merge together in a more conventional process) ([0053]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Chou in further view of Shih (Wu/Chou/Shih) as applied to claim 6 above, and further in view of Orr et al., US PGPub 2023/0089495 (hereinafter referred to as “Orr”).
Regarding Claim 7, Wu/Chou/Shih disclose the method of claim 6, as discussed above.
Wu, Chou, and Shih are silent on further comprising depositing a dielectric layer on the first semiconductor material, wherein the second semiconductor material is deposited on the dielectric layer.
However, Orr, which is directed to novel configurations of nanowire/ribbon/sheet channels and arrangements of fin structures and related portions therein, teaches a dielectric layer on the first semiconductor material, wherein the second semiconductor material is deposited on the dielectric layer (FIGs. 1a, 5c, dielectric layer 105 on source or drain region 103, source or drain region 107 on dielectric layer 105; [0029]). Orr teaches that stacking such semiconductor materials in the well portions (i.e., source/drain regions) is beneficial for electrically separating source/drain epitaxial layers, such as in the case of forming vertical PN junctions ([0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu/Chou/Shih with the teachings of Orr to further comprising depositing a dielectric layer on the first semiconductor material, wherein the second semiconductor material is deposited on the dielectric layer, for the benefit of providing electrical separation between source/drain epitaxial layers ([0029]).
Claims 8-11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chou and further in view of Min et al., US Patent No. 10153358 B2 (hereinafter referred to as “Min”).
Regarding Claim 8, Wu discloses a method (FIG. 3A, method 100; [0030]), comprising:
forming a fin structure from a substrate (FIG. 6, operation 106, fin structures 29; [0037]);
depositing an insulating material around the fin structure ([0038]);
recessing the insulating material (FIG. 7, operation 108, isolation insulating layer 15; [0041]);
forming a sacrificial gate structure over a first portion of the fin structure (FIG. 8, operation 110, sacrificial gate structure 49; [0042]),
wherein a first portion of the insulating material is covered by the sacrificial gate structure (as indicated by the red arrow annotation in FIG. 8 above), and a second portion of the insulating material is exposed (as indicated by the teal arrow annotation in FIG. 8 above);
depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure (FIG. 9, operation 112, cover layer 40; [0045]),
and recessing the second portion of the fin structure (FIG. 11A, operation 114, forming S/D trench 27; [0048]).
Wu is silent regarding performing a plasma etch process to etch the second portion of the insulating material, wherein a recess is formed in the second portion of the insulating material adjacent the fin structure.
However, as discussed above with regards to Claim 1, Chou teaches modifying, or recessing, the exposed portion of the insulating material adjacent the fin structure to obtain different potential surface topologies for the benefits of correcting unwanted etching occurring during the patterning of the sacrificial gate and/or to give control of “active region and/or epitaxial growth shapes that improve the performance of the FinFET structure” (Chou FIGs. 7C-7C, 8A-8C, isolation regions 316a, 316b; [0027, 0050-0055, 0058-0061, 0066].
Chou’s process is a two-step process of tilt ion implantation and a subsequent wet etch and does not explicitly teach that such modification be accomplished through plasma etching.
However, Min, which is directed to a similar method of manufacturing FinFETs, teaches that a plasma etch process can be used to etch insulating material to form STI, wherein the formed STI is of the same material possibilities as detailed in the instant specification and both Wu and Chou (Col 6 lines 20-29, Col 6 lines 62 to Col 7 line 22). Specifically, Min teaches using a plasma etch process to modify the surface of insulating material provides the benefit of enhanced selectivity compared to wet etches (Col 7 line 59 to col 8 line 3, Col 8 lines 9 to 23) and thus prevent process defects by controlling unwanted excessive etching (FIGs. 13A-13B; Col 8 line 49 to Col 9 line 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu with the modification teachings of Chou, which teaches modifying the shape of the exposed insulation region surface for the benefit of controlling the shape of the active region/epitaxial growth shapes for improved FinFET performance, and the plasma etch teachings of Min, for the benefit of enhanced selectivity over wet etches and thus improved defect reduction by controlling unwanted excessive etching, resulting in performing a plasma etch process to etch the second portion of the insulating material, wherein a recess is formed in the second portion of the insulating material adjacent the fin structure.
Further, in such a combined method, the teachings of Wu of depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure would thus result in wherein the first spacer is deposited in the recess in the second portion of the insulating material formed from the combined teachings of Wu/Chou/Min as described above.
Regarding Claim 9, Wu/Chou/Min discloses the method of claim 8, as discussed above.
Min further discloses wherein the plasma etch process utilizes a main etchant and a secondary etchant (Col 6 lines 20-29, Col 6 line 62 to Col 7 line 22).
Regarding Claim 10, Wu/Chou/Min discloses the method of claim 9, as discussed above.
Min further discloses wherein the main etchant comprises CF-4, and the secondary etchant comprises Ar (Col 6 lines 20-29, Col 6 line 62 to Col 7 line 22).
Regarding Claim 11, Wu/Chou/Min discloses the method of claim 10, as disclosed above.
Min further discloses wherein the plasma etch process comprises pulsing a bias voltage (FIGs. 11, 12; Col 7 line 59 to Col 8 line 3, Col 8 lines 9-23).
Regarding Claim 13, Wu/Chou/Min discloses the method of claim 8, as disclosed above.
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Wu further discloses wherein the first portion of the insulating material includes a first top surface having a first center top surface and a first edge top surface (see further annotated FIG. 8 below, wherein the red solid lined box points to the first center top surface of the covered portion of the isolation insulating layer 15 and the red dashed lined box points to the first edge top surface of the covered portion of the isolation insulating layer 15).
Regarding Claim 14, Wu/Chou/Min discloses the method of claim 13, as disclosed above.
Chou further discloses wherein a first angle formed between the first center top surface and the first edge top surface is an obtuse angle (FIG. 8A, Θsw1(post); [0061]).
Regarding Claim 15, Wu/Chou/Min discloses the method of claim 14, as disclosed above.
Chou further discloses wherein the second portion of the insulating material includes a second top surface having a second center top surface and a second edge top surface (see annotated FIG. 9A below, teal solid arrow points to a second center top surface and teal dashed arrow points to a second edge top surface; [0061])
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Regarding Claim 16, Wu/Chou/Min discloses the method of claim 15, as discussed above.
Chou further discloses wherein a second angle formed between the second center top surface and the second edge top surface is an acute angle (FIG. 8C, Θsw3(post); [0061])
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chou and further in view of Min (Wu/Chou/Min) as applied to claim 8 above, and further in view of Yin et al., US PGPub 2015/0235854 A1 (hereinafter referred to as “Yin”).
Regarding Claim 12, Wu/Chou/Min discloses the method of claim 8, as discussed above.
Neither Wu nor Chou nor Min explicitly disclose wherein the sacrificial gate structure is formed by a wet etch process; rather, for example, Wu only discloses that a “patterning method” is used to form the sacrificial gate but gives no further information on the exact type of patterning method.
However, Yin, which is directed to methods of forming and fabricating sacrificial dummy structures, teaches that sacrificial or dummy gates can be formed via wet etch processes (FIGs. 2, 8, gate pattern 3P; [0029]). Yin teaches that a wet etching process to pattern and form the sacrificial gate structures provides the benefit of vertical side-walls, good etch selectivity, less rough gate line surfaces, and reduced or no corner etching at the bottom of the formed structure ([0004, 0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Wu/Chou/Min with the teachings of Yin wherein the sacrificial gate structure is formed by a wet etch process for the benefit of vertical side-walls, reduced or no corner etching, and less rough line surfaces ([0004, 0029]).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chou.
Regarding Claim 17, Wu discloses a method (FIG. 3A, method 100; [0030]), comprising:
forming a fin structure from a substrate (FIG. 6, operation 106, fin structures 29; [0037]);
depositing an insulating material around the fin structure ([0038]);
recessing the insulating material (FIG. 7, operation 108, isolation insulating layer 15; [0041]);
forming a sacrificial gate structure over a first portion of the fin structure (FIG. 8, operation 110, sacrificial gate structure 49; [0042]),
wherein a first portion of the insulating material is covered by the sacrificial gate structure (as indicated by the red arrow annotation in FIG. 8 above), and a second portion of the insulating material is exposed (as indicated by the teal arrow annotation in FIG. 8 above);
and the first portion of the insulating material includes a first top surface having a first center top surface (see further annotated FIG. 8 above, wherein the red solid lined box points to the first center top surface of isolation insulating layer 15) and a first edge top surface (see further annotated FIG. 8 above, wherein the red dashed lined box points to the first edge top surface of isolation insulating layer 15),
wherein a highest point of the first edge top surface is at a level substantially higher than a highest point of the first center top surface (see further annotated FIG. 8 above, wherein there is a clear slope to the surface of isolation insulating layer 15 such that the highest point of the edge top surface is at a level “substantially” higher than a highest point of the center top surface);
and depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure (FIG. 9, operation 112, cover layer 40; [0045]).
Wu is silent regarding modifying a second top surface of the exposed second portion of the insulating material, wherein the second top surface includes a second center top surface and a second edge top surface, and a highest point of the second edge top surface is at a level substantially the same as a highest point of the second center top surface.
However, Chou, which is directed to a similar manufacture of FinFET and Gate-All-Around structures teaches that one can use a combination of tilt ion implantation and etching to modify the surface of isolation regions, even after the formation of the sacrificial dummy gate (wherein the requisite formation steps cause damage or unwanted etching of the exposed isolation regions), to control the topography of the isolation region surface from concave to convex to flat, i.e., to modify a second top surface of the isolation region to have a center and edge top surfaces wherein that center and edge can be modified to be level or flat or, necessarily, at a “level substantially the same” (Chou FIGs. 7C-7D, 8A-8C, isolation regions 316a, 316b, see annotated FIG. 8B below, with solid teal arrow indicating a center top surface and dashed teal arrow indicating an edge top surface of the exposed isolation region; [0050-0055, 0058-0061, 0066]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu with the teachings of Chou of modifying a second top surface of the exposed second portion of the insulating material, wherein the second top surface includes a second center top surface and a second edge top surface, and a highest point of the second edge top surface is at a level substantially the same as a highest point of the second center top surface for the benefit of control of the shape of the exposed isolation region surface from concave to convex to flat, allowing for control of “active region and/or epitaxial growth shapes that improve performance of the FinFET structure” [0061].
Regarding Claim 18, Wu/Chou discloses the method of claim 17, as discussed above.
Wu further discloses further comprising depositing a second spacer on the first spacer (FIG. 9, additional cover layer 47; [0046]).
Regarding Claim 19, Wu/Chou discloses the method of claim 18, as discussed above.
Wu further discloses further comprising removing horizontal portions of the first and second spacers and recessing a second portion of the fin structure (FIG. 10A to FIG. 11A, see figures above from discussion of Claim 3, showing horizontal portions of cover layer 40, and thus additional cover layer 47 (not shown in figure), in FIG. 10A and [0047], as indicated by the red dashed box annotations, which are then etched (removed) in FIG. 11A, operation 114 (note red dashed box annotations in S/D trench 27 indicating horizontal portions of cover layer 40 has been removed). As the horizontal portions are directly on top of the semiconductor layers 20 and 25 to be etched (i.e., exposed fin structure 29), the spacers must necessarily be etched (removed) prior to recessing the exposed fin structure 29).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu/Chou as applied to Claim 17 above, and further in view of Min.
Regarding Claim 20, Wu/Chou disclose the method of claim 17, as discussed above.
Neither Wu nor Chou disclose wherein the second top surface is modified by a plasma etch process.
However, Min, as discussed above with regards to Claim 8, teaches that a plasma etch process can be used to etch insulating material to form STI, wherein the formed STI is of the same material possibilities as detailed in the instant specification and both Wu and Chou (Col 6 lines 20-29, Col 6 lines 62 to Col 7 line 22). Specifically, Min teaches using a plasma etch process to modify the surface of insulating material provides the benefit of enhanced selectivity compared to wet etches (Col 7 line 59 to col 8 line 3, Col 8 lines 9 to 23) and thus prevent process defects by controlling unwanted excessive physical etching (FIGs. 13A-13B; Col 8 line 49 to Col 9 line 9). Further, such an etching process would therefore provide modification of the insulating material in one step, rather than the two-step process as disclosed in Chou (the tilt ion implantation followed by subsequent wet etching) and thus provide a benefit in increasing manufacturing efficiency.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu/Chou with the plasma etch of insulating material teachings of Min such that wherein the second top surface is modified by a plasma etch process for the benefit of enhanced selectivity, preventing process defects, and increasing manufacturing efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hsu, US PGPub 2022/0285531 A1, which is directed to a similar FinFET structure surrounding the source and drain, but achieved using an additional layer on the STI, and subsequent patterning of such using a similar plasma etch chemistry.
Liu et al., US PGPub 2022/0059679 A1, which is directed to fin formation in FinFETs using similar plasma etch chemistries as in the instant application to pattern both the fins and the isolation regions.
Shiao et al., US PGPub 2016/0351669 A1, which is directed to a similar FinFET structure and manufacture thereof, wherein much detail is provided about a similar plasma etch chemistry when used to etch isolation material.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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