DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/05/2024 is being considered by the examiner.
Drawings
The drawings submitted on 04/05/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US0120299117 A1) in view of Kai et al. (US 20190027488 A1).
Regarding claim 1, Lee discloses a memory device, comprising:
a stacked body (from layers 110 to 112A in Fig. 7F) including interlayer insulating layers (112A) and conductive layers (113A) alternately stacked with one another in a first direction (y-direction); ([0103]-[0104], Fig. 7F)
a channel layer (116A) penetrating the stacked body; ([0098], Fig. 7F)
a tunnel isolation layer (115A) enclosing an outer side surface of the channel layer (116A) and having a first thickness; ([0098], Fig. 7F)
a liner layer (120A) extending along a top surface of the stacked body and at least a portion of an outer side surface of the spacer (119A).
Lee does not disclose:
a capping layer extending from the channel layer and protruding from the stacked body in the first direction;
a spacer enclosing an outer side surface of the capping layer on the stacked body and having a second thickness greater than the first thickness;
However, Kai discloses:
a capping layer (162) extending from the channel layer (60) and protruding from the stacked body in the first direction (y-direction); (Fig.20)
a spacer (182+175) enclosing an outer side surface of the capping layer (162) on the stacked body and having a second thickness greater than the first thickness; ([0150], [0172], Fig. 24A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for a capping layer extending from the channel layer and protruding from the stacked body in the first direction; a spacer enclosing an outer side surface of the capping layer on the stacked body and having a second thickness greater than the first thickness so that “ the drain select level isolation strips (120, 270) can be formed without using any additional footprint in the design layout of the three-dimensional memory device, thereby providing a higher density three-dimensional memory devices without alteration of an inter-row pitch used to form prior art drain select level isolation structures.” (Kai, [0302])
Regarding claim 2, Kai discloses the memory device according to claim 1, wherein:
the capping layer (162) comprises a first portion (annotated below) located inside the stacked body and a second portion protruding from the stacked body in the first direction (y-direction), the first portion is enclosed by the channel layer (60), and the second portion is enclosed by the spacer (182+175). (Fig. 24A)
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Regarding claim 3, Kai discloses the memory device according to claim 2, further comprising: a core pillar (62) disposed under the first portion (annotated above) and enclosed by the channel layer (60). (Fig. 24A)
It would’ve been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for similar reasons mentioned beforehand.
Regarding claim 4, Kai discloses the memory device according to claim 3, wherein a top surface of the core pillar (62) is located lower than the top surface (above 70) of the stacked body. (Fig. 24A)
It would’ve been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for similar reasons mentioned beforehand.
Regarding claim 5, Lee discloses the memory device according to claim 1, further comprising:
a protective layer (122) covering a top surface of the capping layer (118). (Fig. 7F)
Regarding claim 6, Lee discloses the memory device according to claim 1, wherein:
the spacer (119A) has a first height in the first direction (y-direction), and the liner layer (120A) has a second height in the first direction (x-direction) lower than the first height in the first direction. (Fig. 7F)
Regarding claim 7, Lee discloses the memory device according to claim 1, wherein:
the liner layer (120A) encloses a portion of the outer side surface of the spacer (119A), and another portion of the outer side surface of the spacer is externally exposed by the liner layer (120A). (Fig. 7F)
Regarding claim 8, Lee discloses the memory device according to claim 1, wherein:
the liner layer (120A) is a drain select line (per [0102]), and each of the conductive layers (113A) is a word line (per [0102]) or a source select line. (Fig. 7F)
Regarding claim 9, Kai discloses the memory device according to claim 1, wherein:
the channel layer (60), the tunnel isolation layer (56), the capping layer (162), and
the spacer (182/175) are included in a first cell plug (annotated below), the liner layer (annotated 152 below) is a first drain select line, and
the memory device further comprises a second cell plug (annotated below) spaced apart from the first cell plug (annotated below) in a second direction (x-direction) of the first cell plug, and a second drain select line (annotated 152 below) spaced apart from the first drain select line (annotated 152 below) in the second direction (x-direction) of the first drain select line. (Fig. 24A)
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It would’ve been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for similar reasons mentioned beforehand.
Regarding claim 10, Kai discloses the memory device according to claim 9, wherein the first drain select line (annotated 152 above) and the second drain select line (annotated 152 above) are separated from each other. (Fig. 24A)
It would’ve been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for similar reasons mentioned beforehand.
Regarding claim 11, Kai Fig. 24 discloses the memory device according to claim 9. Kai Fig. 24A does not disclose wherein a portion of the top surface of the stacked body is exposed between the first drain select line and the second drain select line.
However, Kai’s Fig. 40 discloses:
a portion of the top surface of the stacked body is exposed between the first drain select line (252 inside first cell) and the second drain select line (252 inside second cell). ([0259], Fig. 40)
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It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Kai for a portion of the top surface of the stacked body is exposed between the first drain select line and the second drain select line so that “a conformal conductive material layer can be conformally deposited on the outer sidewalls of the gate dielectrics 250, on the top surface of the topmost insulating layer 32, and the top surfaces of the vertical semiconductor channels 60” (Kai, [0240]) “thereby providing a higher density three-dimensional memory device” (Kai, [0302])
Regarding claim 12, Kai discloses the memory device according to claim 9, further comprising: a source line (46) disposed under the stacked body. ([0190], [0206], Fig. 28)
It would’ve been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Kai for similar reasons mentioned beforehand.
Regarding claim 13, Kai discloses the memory device according to claim 12. Kai does not disclose wherein the source line comprises:
a first sub-source line coupled to the first cell plug; and
a second sub-source line coupled to the second cell plug.
However, Lee discloses:
wherein the source line (43B) comprises:
a first sub-source line (43B) coupled to the first cell plug (left side stack); ([0055], Fig. 4F) and
a second sub-source line (43B) coupled to the second cell plug (right side stack). ([0055], Fig. 4F)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kai and Lee for the source line comprises: a first sub-source line coupled to the first cell plug; and a second sub-source line coupled to the second cell plug so that “selection gates may be prevented from being removed in an etch process for separating word lines from one another.” (Lee, [0140])
Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20150243672 A1) in view of Baraskar et al. (US 101115730 B1) and Lee et al. (US 20120299117 A1).
Regarding claim 14, Kim discloses a method of manufacturing a memory device, comprising:
forming a preliminary channel layer (227) penetrating a stacked body (layers up to 205), and a tunnel isolation layer (225) enclosing an outer side surface of the preliminary channel layer (227), wherein the tunnel isolation layer (225) has a first thickness; (Fig. 2A)
forming a preliminary capping layer (231) contacting a top of the preliminary channel layer (227); ([0038], Fig. 2A)
exposing a portion of the preliminary channel layer (227) by removing an upper portion (235) of the stacked body (layers up to 205); ([0040], Fig. 2A)
Kim does not disclose:
forming a spacer having a second thickness greater than the first thickness by oxidizing the exposed preliminary channel layer and the preliminary capping layer; and
forming a liner layer extending along a top surface of the stacked body and the spacer.
However, Baraskar discloses:
forming a spacer (116) having a second thickness greater than the first thickness (of 56) by oxidizing the preliminary capping layer (142); (col. 24, lns. 65-67, Fig. 14A-14C)
Baraskar does not explicitly disclose the exposed preliminary channel layer
However, Baraskar discloses:
“Alternatively, if the annular silicon oxide spacer 116 is formed by oxidation of the pedestal channel portion 11 through the backside recess 143, then the pedestal channel portion 11 can be made thicker to avoid over-narrowing it during the oxidation. The pedestal channel portion can be made thicker by selectively widening the bottom part of the memory opening 49 followed by growing the thicker pedestal channel portion 11 in the widened bottom part of the memory opening 49, as illustrated in FIGS. 14A-14E and FIGS. 21A-22C.” ([col. 32, lns. 56-65])
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kim and Baraskar for forming a spacer having a second thickness greater than the first thickness by oxidizing the exposed preliminary channel layer and the preliminary capping layer in order to “avoid over-narrowing it during the oxidation”. (Baraskar, [col. 32, lns. 56-65])
and Lee discloses:
forming a liner layer (51) extending along a top surface of the stacked body (layers up to 45A) and the spacer (50). (Fig. 4F)
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Kim, Baraskar and Lee to arrive at the claimed invention so that “RC delay may be improved by increasing an interval between a selection gate line and a word line.” (Lee, [0142])
Regarding claim 15, Kim discloses the method according to claim 14, wherein forming the preliminary channel layer (227) and the tunnel isolation layer (225) comprises:
forming a core pillar (229) enclosed by the preliminary channel layer (227). (Fig. 2A)
Regarding claim 16, Kim discloses the method according to claim 15, wherein forming the preliminary capping layer (231) comprises:
removing a portion (237) of the core pillar (229); ([0042], Fig. 2C)
and filling a region (237) in which the core pillar (229) is removed with the preliminary capping layer (241). (Fig.2A-2C)
Regarding claim 17, Lee discloses the method according to claim 14, further comprising, after forming the preliminary capping layer (118):
forming a protective layer (121) on a top surface of the preliminary capping layer (118). (Fig. 7F)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for forming a protective layer on a top surface of the preliminary capping layer so that “selection gates may be prevented from being removed in an etch process for separating word lines from one another.” (Lee, [0140])
Regarding claim 18, Lee discloses the method according to claim 17, wherein forming the liner layer (120) comprises:
forming a preliminary liner layer (120) on the top surface of the stacked body (layers up to 112), the spacer (119),
forming the liner layer (120A) having a height lower than a height of the spacer (119A) by removing a portion of the preliminary liner layer (120). (Fig. 7E-7F)
Lee does not disclose:
forming a preliminary liner layer (120) on the top surface of the protective layer (121)
However, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a preliminary liner layer on the top surface of the protective layer, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 19, Lee discloses the method according to claim 18, wherein forming the liner layer (120A) comprises:
exposing a portion of the top (side) surface of the stacked body (layers up to 112A) by removing a portion of the preliminary liner layer (120). (Fig. 7E-7F)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Lee for exposing a portion of the top surface of the stacked body by removing a portion of the preliminary liner layer so that “selection gates may be prevented from being removed in an etch process for separating word lines from one another.” (Lee, [0140])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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