DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11-14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/20/2026.
Applicant’s election without traverse of Group I, claims 1-10 and 15-20 in the reply filed on 7/20/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "a height of the first upper area and the second upper area" in line 2. It is not clear how an area can have a height. Accordingly, the boundaries of the claims are not reasonably clear and also language in the claims is ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention. Note; For the purpose of examination, the examiner interprets the limitation "a height of the first upper area and the second upper area" as "a height of the first and second electrode at the first upper area and the second upper area".
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karasawa , JP 2021-005683.
Regarding claim 1, Karasawa discloses; A semiconductor package comprising: a package substrate (Fig. 1-7; circuit board 100); a ceramic electronic component electrically connected to the package substrate (Fig. 1-7; chip resistor 10 is made of ceramics and mounted on the circuit board 100 by soldering), the ceramic electronic component including a main body having a main body upper surface (Fig. 1-7; upper surface of chip resistor 10), a first electrode disposed on a first side of the main body (Fig. 1-7; surface electrode 2 and end face electrode 6 on the left side of chip resistor 10), the first side of the main body including a first upper area disposed on the main body upper surface (Fig. 1-7; the area under left surface electrode 2 on the upper surface of chip resistor 10), and a second electrode disposed on a second side of the main body that is opposite to the first side of the main body (Fig. 1-7; surface electrode 2 and end face electrode 6 on the right side of chip resistor 10), the second side of the main body including a second upper area disposed on the main body upper surface (Fig. 1-7; the area under right surface electrode 2 on the upper surface of chip resistor 10), the second upper area is spaced apart from the first upper area (Fig. 1-7; the area under left and right surface electrode 2 are space apart); a protection unit disposed on the main body upper surface and positioned between the first upper area and the second upper area (Fig. 1-7 and abstract; first protective layer 4 and the resistive element 3); and a mold unit sealing the ceramic electronic component and the protection unit (Fig. 1-7; the second protective layer 7 on the surface of the insulating substrate 1. Not only does it cover the entire surface, but it is also formed to a position where it wraps around to the end surface of the insulating substrate 1 and covers a part of the end surface electrode 6).
Regarding claim 2, Karasawa discloses; a length of a lowermost portion of the protection unit is less than or equal to a distance between the first upper area and the second upper area (Fig. 1-7; length of the resistive element 3 is equal to a distance between the left and right surface electrode 2).
Regarding claim 3, Karasawa discloses; the protection unit covers at least a portion of an upper surface of the first upper area (Fig. 1-7; first protective layer 4 and the resistive element 3 cover at least a portion of an upper surface of the left surface electrode 2).
Regarding claim 4, Karasawa discloses; the protection unit covers at least a portion of an upper surface of the second upper area (Fig. 1-7; first protective layer 4 and the resistive element 3 cover at least a portion of an upper surface of the right surface electrode 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Karasawa, JP 2021-005683 as applied to claims 1-4 above, and further in view of JEONG, US 2022/0208468.
Regarding claims 5 and 6, Karasawa substantially discloses the invention including protective and resistive element between upper electrodes for a chip resistor but is silent about sides of an uppermost portion of the first electrode are not in direct contact with the protection unit in claim 5 and sides of an uppermost portion of the second electrode are not in direct contact with the protection unit in claim 6. However, JEONG shows that protective layer at the region 345 are separated from the first and second electrode layer 331a and 332a (Fig. 7). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Karasawa by providing sides of an uppermost portion of the first electrode are not in direct contact with the protection unit in claim 5 and sides of an uppermost portion of the second electrode are not in direct contact with the protection unit in claim 6, so that the protective layer of the multilayer ceramic electronic component according to the present disclosure include a polyfunctional alkoxy silane. Since the alkoxy silane has hydrophobicity, moisture penetration and contamination can be prevented, and flexural stress mechanical strength can be improved through a curing reaction [0053].
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Karasawa, JP 2021-005683 as applied to claims 1-4 above, and further in view of Kayatani, US 2004/0240146.
Regarding claim 10, Karasawa substantially discloses the invention including protective and resistive element between upper electrodes of a chip resistor but is silent about the ceramic electronic component is a multi-layer ceramic capacitor. However, Kayatani teaches that the monolithic ceramic capacitor 10 is mounted on the substrate 30 such that the thermoplastic resin layer 22 covers substantially the entire surface except for the solder parts of the monolithic ceramic capacitor 10 (Fig. 3 and [0036]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Karasawa by providing the ceramic electronic component is a multi-layer ceramic capacitor, so that a multilayer ceramic electronic component is prepared by covering a capacitor element with a thermoplastic resin layer that is mounted on a substrate by soldering (abstract).
Claim(s) 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Karasawa, JP 2021-005683, and further in view of Lim, US 2008/0180919.
Regarding claims 15 and 16, Karasawa discloses in claim 15; A semiconductor package comprising: a package substrate (Fig. 1-7; circuit board 100); a ceramic electronic component electrically connected to the package substrate (Fig. 1-7; chip resistor 10 is made of ceramics and mounted on the circuit board 100 by soldering), the ceramic electronic component including a main body having a main body upper surface (Fig. 1-7; upper surface of chip resistor 10), a first electrode disposed on a first side of the main body (Fig. 1-7; surface electrode 2 and end face electrode 6 on the left side of chip resistor 10), the first side of the main body including a first upper area disposed on the main body upper surface (Fig. 1-7; the area under left surface electrode 2 on the upper surface of chip resistor 10), and a second electrode disposed on a second side of the main body that is opposite to the first side of the main body (Fig. 1-7; surface electrode 2 and end face electrode 6 on the right side of chip resistor 10), the second side of the main body including a second upper area disposed on the main body upper surface (Fig. 1-7; the area under right surface electrode 2 on the upper surface of chip resistor 10), the second upper area is spaced apart from the first upper area (Fig. 1-7; the area under left and right surface electrode 2 are space apart); a protection unit disposed on the main body upper surface and positioned between the first upper area and the second upper area (Fig. 1-7 and abstract; first protective layer 4 and the resistive element 3); and a mold unit sealing the ceramic electronic component and the protection unit (Fig. 1-7; the second protective layer 7 on the surface of the insulating substrate 1. Not only does it cover the entire surface, but it is also formed to a position where it wraps around to the end surface of the insulating substrate 1 and covers a part of the end surface electrode 6). Karasawa substantially discloses the invention including protective and resistive element between upper electrodes of a chip resistor but is silent about at least one semiconductor chip in claim 15 and a controller disposed on the package substrate, the controller controls the semiconductor chip in claim 16. However, Lim teaches that a semiconductor module 700 include a plurality of semiconductor chips 152 and 180 and passive devices 54, mounted on a substrate 50. Semiconductor chip 152 a memory chip, and semiconductor chip 180 a controller chip (Fig. 7 and [0030]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Karasawa by providing at least one semiconductor chip in claim 15 and a controller disposed on the package substrate, the controller controls the semiconductor chip in claim 16, so that a semiconductor module (e.g., memory card, multimedia card, central processing unit, multi-chip package) include a semiconductor chip mounted on a module substrate structure with one or more passive devices mounted on the module substrate structure as interfaces for the semiconductor chip and application devices [0005].
Regarding claim 17, Karasawa discloses; a length of a lowermost portion of the protection unit is less than or equal to a distance between the first upper area and the second upper area (Fig. 1-7; length of the resistive element 3 is equal to a distance between the left and right surface electrode 2).
Regarding claim 18, Karasawa discloses; a height of the protection unit is twice or more greater than a height of the first upper area and the second upper area (Fig. 1-7 and abstract; the height of first protective layer 4 and the resistive element 3 is greater than the height of left and right surface electrode 2).
Regarding claim 19, Karasawa discloses; the protection unit covers at least a portion of an upper surface of the first upper area (Fig. 1-7; first protective layer 4 and the resistive element 3 cover at least a portion of an upper surface of the left surface electrode 2).
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Karasawa, JP 2021-005683, in view of Lim, US 2008/0180919, as applied to claims 15-19 above, and further in view of JEONG, US 2022/0208468.
Regarding claim 20, Karasawa substantially discloses the invention including protective and resistive element between upper electrodes for a chip resistor but is silent about sides of an uppermost portion of the first electrode and sides of an uppermost portion of the second electrode are not in direct contact with the protection unit. However, JEONG shows that protective layer at the region 345 are separated from the first and second electrode layer 331a and 332a (Fig. 7). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Karasawa by providing sides of an uppermost portion of the first electrode and sides of an uppermost portion of the second electrode are not in direct contact with the protection unit, so that the protective layer of the multilayer ceramic electronic component according to the present disclosure include a polyfunctional alkoxy silane. Since the alkoxy silane has hydrophobicity, moisture penetration and contamination can be prevented, and flexural stress mechanical strength can be improved through a curing reaction [0053].
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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