CTNF 18/627,789 CTNF 100229 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings The drawings submitted on June 18 th , 2024 have been considered and are objected to by the examiner. The drawing is objected to under 37 CFR 1.83(a) and MPEP 608.02 because reference character 901 in Figure 12 designates a top/horizontal portion of the spacer structure, whereas the same reference character 901 is defined in the specification and depicted in Figures 9, 10A, and 11 as the first spacer remaining along a sidewall of first facet 701 after liner removal processes remove the horizontal portions of the first spacer material 801. A reference character must designate the same part throughout (MPEP 608.02 section VII). In Figure 12, element 901 instead points to a region that would have had the spacer material removed – directly contradicting Figures 8-9. Correction is required so that Figure 12 designates the sidewall spacer consistently with the remainder of the disclosure. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-14 and 19-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 07-34-12 Claims 1, 2, 8 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The specification describes a method of manufacturing an optical device which comprises at least 10 steps, each having sub-steps: Step 1: generally shown in fig. 1 describes preparing an optical interposer 100 including a first substrate 101, forming all of the various layers, 103, 107, 115, etc., and creating the first opening 125. This step includes the formation of through device vias (TDVs) 118 at any point during metallization layer formation, as described in paragraph 35. Step 2: generally shown in fig. 2 describes filling the first opening 125 with gap-fill material 201. Step 3: generally shown in fig. 3 describes bonding a semiconductor device 301 to the optical interposer 100 and providing a second gap-fill material 313 to fill the space around the semiconductor device 301. Step 4: generally shown in figs. 4 and 5 describes the attachment of support substrate 401 to the semiconductor device 301 and gap-fill material 313 and removing the first substrate 101. Step 5: generally shown in figs. 6A and 6B describes adding layers 604, 605, 607 and 609 to the optical interposer 100 side of the device and then forming openings 611 over TDVs 118. Step 6: generally shown in fig. 7 describes forming a first facet 701 by removing a portion of the optical interposer layers and semiconductor device layers from the sidewall of the partially formed device, while not removing any of the supporting substrate layer 401. Step 7: generally shown in figs. 8-9 describes forming the first spacer along the first facet 701 by depositing a first spacer material 801 to line the first facet 701 and the second openings 611 (paragraph 62). Then, a liner removal process is performed to remove the horizontal portions of the first spacer material 801, exposing the first TDVs 118 through the first buffer layer 604, and leaving the first spacer 901 along the sidewall of the facet. Step 8: generally shown in figs. 10A-10C describes forming a redistribution structure over the optical interposer 100 side of the device, including a sixth passivation layer 10001, a first redistribution layer 1003 having conductive elements formed outside a keep-out zone 1021, a seal ring 10004 and a dummy portion 1006 within the keep-out zone 1021, a seventh passivation layer 1005, second contact pads 1007, and first external connections 1009. Step 9: generally shown in figs. 10A-11 describes forming the first facet 701 and scribe region 705 (offsetting the facet sidewall from the second edge coupler 116 by a first spacing S1) and singulating the structure through the scribe region 705 by, e.g., sawing through the support substrate 401. Step 10: generally shown in fig. 13 describes bonding the first redistribution layer 1003 to a substrate 1301 through the first external connections 1009, placing a first underfill 1303 around the first external connections 1009, and attaching a fiber array unit 1406 aligned with the first edge coupler 111 and/or second edge coupler 116. Regarding claim 1: Claim 1 includes four method steps. The first step “receiving” describes the intermediate partially formed structure as disclosed which is a result of performing steps 1-3 from above, however steps 1-3 from above are not recited in claim 1. It this has an “attaching” a support substrate which is a part of step 4 from above. Next the claim recites “forming a facet recess to recess a sidewall of the first optical interposer and expose the support substrate” which is step 6 above, and lastly the claim recites “forming a first spacer” which step 7 above. Claim 1 is missing essential claimed elements, such as most of steps 1-3 which describe how the partially formed intermediate device is formed prior to the first method step of claim 1. Claim 1 also does not include needed details such as forming the second gap-fill material 313 around the semiconductor device, which is essential because it is part of this material which is removed when forming the facet recess in the third method step of claim 1. Further claim 1 does not include removing the first substrate 101. Because claim 1 does not have many of the previously performed steps, it is unclear in the “forming a facet recess” step, what layers, or portions of layers are actually removed. In general , because claim 1 is missing essential steps it is impossible for one skilled in the art to understand what the claimed method is trying to capture. Claims 2-7 are also indefinite as they are dependent on claim 1 and inherit its indefiniteness. Regarding claim 2: Claim 2 depends from claim 1 and recites that the forming of the first spacer further comprises “depositing a first buffer layer over a through device via; depositing a first passivation layer over the first buffer layer ... performing a liner removal process to expose the through device via and form the first spacer.” These sub-steps correspond to steps 5-7 above. However, claim 2 presupposes the first TDVs 118 (Figures 6A-9), and forming the first buffer layer over the openings 611 above said through device vias is predicated on this presupposition. As in paragraph 35, the TDVs can be formed at any time during the manufacturing of the metallization layers in step 1. However, no claim language is directed towards the formation of a metallization layer. Thus, the step in which TDVs are formed is not present. The claim is therefore incomplete for omitting an essential step, amounting to a gap between the recited steps; the first mention of the metallization layers that are concomitant with the formation of TDVs is in claim 4. Regarding claim 8: Claim 8 recites a method of manufacturing an optical device including forming a first opening (step 1), first gap fill material in said opening (step 2), bonding a first semiconductor to the metallization layer and depositing a second gap fill materials (steps 2-4), removing portions of gap fills to form a first facet and forming a first spacer along a sidewall of the first facet (step 6). Claim 8 does not explain what device that “removing a first portion of a metallization layer” is being performed on. This step corresponds to step 1 above where a first portion of a metallization layer of the optical interposer is removed. The disclosed method also requires removal the first substrate 101 after the support substrate 401 is attached, which corresponds to step 4 above. This step is not described in claim 8. This step is essential because the optical interposer in which claim 8’s first facet 701 is formed establishes the structure for the first spacer and is the remaining structure after the first substrate 101 is removed. Claim 8 proceeds directly from “bonding a support substrate to the second gap fill material” (step 4) to “after the bonding the support substrate, removing portions of the first gap fill material and the second gap fill material to form a first facet” (step 6), omitting the intervening removal of the first substrate 101. Claim 5 also does not include any details of step 5 above, adding the required insulation layers 604, 605, 607 and 609 to the optical interposer 100 side of the device and then forming openings 611 over TDVs 118. Accordingly, claim 8 is incomplete for omitting an essential step, amounting to a gap between recited steps. Claims 9-14 are indefinite as they depend on claim 8 and inherit its indefiniteness. Appropriate correction is required: amendment of claims 1 and 8 to include essential method steps and ensuring that all independent claims recite all essential method steps is essential to close the gap between recited steps and elucidate the indefiniteness of the claims. Regarding claim 12: Claim 12 recites “wherein the dummy portion is located to reflect light to a grating coupler within the first optical components.” The dummy portion corresponds to step 8, however claim 12 presupposes a structure that is formed by a step that is not claimed. Specifically: Claim 12 recites that the dummy portion reflects light to a grating coupler within the first optical components, yet neither claim 12 nor its parent claims (8, 9, and 10) recite forming a grating coupler or a step associated with forming the grating coupler. The disclosed method form the first grating couplers 1201 as part of the first optical components 109 of the first active layer 107 or as part of the second optical components 17 of the first metallization layers 115, which corresponds to step 1 above. Any claims concerning step 1 in the lineage of claim 12 do not recite the necessary language to indicate how or where a grating coupler should be formed (“In some embodiments the second optical components 117 of the first metallization layers 115 may include such components as couplers [ e.g. , edge couplers, grating couplers, etc.]”). Accordingly, claim 12 is incomplete for omitting an essential step, such omission amounting to a gap between the recited steps. Appropriate correction is required. Claim 13 is indefinite due to being dependent on an indefinite claim. Claims 5-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, for reciting limitations which claims features that lack antecedent basis or being dependent on claims thereof. Regarding claim 5: Claim 5 recites the limitation "…adjacent to the sidewall of the first facet recess " at the end of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 1, from which claim 5 depends, establishes “...forming a facet recess,” but the “first” is never applied to “facet recess” in claim 1, so a skilled artisan cannot determine with reasonable certainty whether the first facet recess refers back to a facet recess of claim 1. Claims 6 and 7 are dependent on claim 5 and are also indefinite. Claims 8-14, 19, and 20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 8: Claim 8 recites the limitations: “depositing a first gap fill material into the first opening,” “depositing a second gap fill material around the first semiconductor device,” “bonding a support substrate to the second gap fill material ,” and “after the bonding the support substrate, removing portions of the first gap fill material and the second gap fill material to form a first facet”. The nature of the ‘gap fill material’ (first or second) is unclear to the examiner, as any material which is used to fill a space can be said to be a gap fill material. The “gap” that is implicitly referred to is also not defined with reasonable certainty. The examiner has looked to the specification for further clarity but still cannot ascertain these terms. Appropriate correction is required. Claims 9-14 are dependent on claim 8 and inherit the indefiniteness with regards to gaps and gap fill materials. Regarding claims 11 and 19: The claims recite the phrases “…layer [forms/comprises] a dummy portion .” Neither claim provides any structural definition, functional characterization, dimensional constraint, or material description of the ‘dummy portion’. The term ‘dummy portion’ has no established plain meaning in the semiconductor packaging art that would inform a skilled artisan of what structure is required or used in the context of the claims; a dummy portion can be many things as long as it is not an active electro-optic component. The dependent claims 12 and 20 do include additional context, but claims 11 and 19 do not recite the additional functional limitations and claim a ‘dummy portion’ in isolation without any context that would give the term definite scope. Applicant may find it efficient to incorporate the functional language of dependent claims 12/20 into the claims 11/19 respectively, or by otherwise defining ‘dummy portion’ with sufficient structural or functional specificity to provide reasonable certainty. Claims 12-13 and 20 are dependent on claims 11 and 19 respectively, and therefore also indefinite. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3, 5, 6, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11404404 B2, hereafter C1) in view of Chen (US 11372160 B2, hereafter C2), and further in view of Shi (US 9787054 B2) . Regarding claim 1: C1 discloses a method of manufacturing an optical device (semiconductor with photonics die, Title), the method comprising: receiving a first optical interposer (photonics wafer PW, Figure 1A, 1F) bonded to a first semiconductor device (electronics die ED, comprising substrate 121, devices 122, interconnect 123 with bonding pads 123c, Figures 1a, and 1f); attaching a support substrate to the first semiconductor device (supporting substrate 210, 310 is disposed over insulating material 130A above the ED, opposite PD, as shown in Figures 4A/B and 6); forming a facet recess (facet 1111f, Figure 1F) to recess a sidewall of the first optical interposer (PD) and expose the support substrate; C1 discloses Figures 1B, 1C, and 1F, which show trenches TR1 etched anisotropically through the layers containing 130A, 115, 114, and 112 into layer 111A producing facet 1111f and smooth sidewalls SW1. Post singulation, top portion 1112 of substrate 111 with width W4 is recessed relative to bottom portion 1111 with width W5 (claims 4-5). In structure 30 (Figure 4B), the supporting substrate (210) overlies the recessed top portion 1112 and is exposed laterally above SW1 at the facet edge. C1 does not explicitly disclose the forming of a first spacer along a sidewall. The use of ‘spacers’ is well established and a ubiquitous practice in the art. A skilled artisan would find it obvious to use spacers for mechanical separation and electrodynamic control. C2 provides the essential methods and process for forming the facet recess in detail (“The etching processes include, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch…”), and using controlled etching with an insulated etch stop layer (Figure 1G, notch N in substrate 110 beneath waveguide tip 140). A skilled artisan would thus be well aware of the methods and benefits of using etching to form recesses, and would be motivated to use etching to produce a tiered substrate geometry wherein singulated trenches are formed with smooth sidewalls (SW) which have less optical loss than non-singulated recesses. Additionally, absent any stated benefit, the depth of the etched trench is a results-effective variable wherein the depth of the trench (say TR1) has a direct, measurable, and predictable/easily modeled outcome and effect on the device’s operation. Too shallow, the wrong method, or too deep and there may be structural damage or loss-inducing defects which impede the function of the device. A skilled artisan would find it obvious to control the etching process and to ensure that it exposed the layers without increasing or causing loss. Shi demonstrates the use of spacers in optical packaging and refers to them with the deference given to well established and known components (i.e. “an optical package may include…a single mode fiber or fiber array assembly, a lens and a spacer,” and further describes that the spacer is bonded to a facet of an edge coupler in a Si PIC, Figure 1, Figure 3 element 330). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in C1 under the teachings of C2 and Shi, to form a facet recess by controlled etching with an insulating stop layer, and to further incorporate the spacer of Shi along the resulting facet sidewall. C1 already established the recessed two-tier substrate geometry (1112/1111 with widths W4 < W5) needed for fiber alignment to facet 1111f along SW1, and C2 solidifies the etch-based notch process with a define etch stop architecture to preserve mechanical integrity. This may be accomplished by using known components (anisotropic dry etch tools, silica/polyimide spacers, support wafers/substrates 210 of C1), known materials, and routine design oversight (placement of spacer along the recessed sidewall) known to a skilled artisan. Predictably, this would result in a device that has a smooth, controlled edge coupling facet with protected optical interface and a defined fiber-to-coupler standoff, resulting in high quality optical connections that suffer from minimal loss. Regarding claim 2: C1 in view of C2 and further in view of Shi teaches the method of claim 1, wherein the forming the first spacer further comprises: depositing a first buffer layer over a through device via (Figure 1A, dielectric layer 114 and interlayer dielectrics of RDL 115b are deposited over through vias 116); C1 does not teach the passivation layer, exposition of buffer layer, spacer material, or the liner removal process as claimed. C2 teaches: depositing a first passivation layer (Figure 1F, a skilled artisan recognizes that the dielectric layer 602 is a passivation/redistribution dielectric, as any reaction inhibitor or insulator is in this context) over the first buffer layer (layer 110 is the buffer layer, but the dielectric is the top layer, any buffer layer would necessarily be below it); exposing the first buffer (“ exposed semiconductor substrate 110”) layer through the first passivation layer (Figure 1G, the substrate 110 is clearly exposed as a result of an etch through the first passivation layer 602); and performing a liner removal process to expose the through device via (Figures 1E-1G, the through vias 160 are exposed via an anisotropic etch sequence to remove the substrate such that the through vias are exposed at a second surface 110b) C2 does not expressly teach depositing a first material for the first spacer; Shi teaches an optical package (Title) wherein spacers are used and shown to be a common component in the art (See rejection of claim 1 above). Shi teaches a first spacer (i.e. spacer 330) as described in the rejection of claim 1 above. Shi teaches a family of materials used for the spacer (“A silica spacer [or isolator] 330 may be bonded…”; “the spacer may include a silica spacer, a glass spacer, a polymer spacer, a polyimide spacer, an epoxy spacer, or a resin spacer.”) Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 1 above under the teachings of C1, C2, and Shi, to dispose a first passivation layer, a first buffer layer, and to expose the buffer layer and through vias using an etching process. Furthermore, a first spacer material is used as taught in Shi, which teaches a set of suitable materials. This may be accomplished using materials (as taught in Shi), components (spacer, various types of layers), and methods known to a skilled artisan, and would predictably result in a device where the electrical properties, electrical access, and optical facet protection can be optimally configured for minimal loss and ease of implementation in mass manufacturing methods. Regarding claim 3: C1 in view of C2 and further in view of Shi teaches the method of claim 2. C1 does not teach the use of silicon nitride, but it is a well-established and known material in the art. C2 teaches the use of silicon nitride in its components (i.e. the dielectric layer 130 may be made from silicon nitride). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 2 above under the teachings of C2 to ensure that a well-established and understood material, silicon nitride, is utilized in the spacer of the device in claim 2. This may be accomplished using readily available and ordinary materials known to a skilled artisan, and would predictably result in a device which contains a spacer that is made from a material with well understood mechanical, chemical, and electromagnetic properties, alongside being cost efficient due to its ubiquitous presence in the industry. Regarding claim 5: C1 in view of C2 and further in view of Shi teaches the method of claim 1, wherein after the forming the facet recess the first optical interposer comprises an edge coupler adjacent to the sidewall of the first facet recess (claim 4, Figure 1F; edge coupler 113 is adjacent to sidewall SW1 formed from facet 1111f). Regarding claim 6: C1 in view of C2 and further in view of Shi teaches the method of claim 5, wherein after the forming the facet recess the first optical interposer (PW) comprises a grating coupler (Figure 1F, “The optical devices 113 may be or may include waveguides, edge couplers, I/O couplers, lasers, optical modulators, detectors, splitters, converters, switches, grating couplers”). The optical device 113 sits below the SW facet and is thus ‘after’ the forming the facet recess. Regarding claim 17: C1 in view of Shi discloses optical device of claim 15. C1 does not teach a redistribution layer as claimed. C2 discloses a first redistribution layer in electrical contact with a metallization layer within the optical interposer. Figure 1F, 1H, redistribution structure 600 with redistribution conductive layers 604 connected to through vias 160 and thus to interconnection structure 150 [this constitutes a metallization layer]. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 15 above under the teachings of C2 to include a first redistribution layer in contact with a metallization layer in the interposer. This may be accomplished using materials and methods (i.e. deposition, etching) known to a skilled artisan and would predictably result in a device wherein optoelectronic function is enabled and signals can be routed between layers in a controlled and low-loss manner . 07-21-aia AIA Claim (s) 4, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11404404 B2, hereafter C1) in view of Chen (US 11372160 B2, hereafter C2), and further in view of Shi (US 9787054 B2) and Pan (US 9780046 B2) . Regarding claim 4: C1 in view of C2 and further in view of Shi teaches the method of claim 1, C1 does not disclose a metallization layer or seal ring as claimed. However, both components are commonly used in the art, metallization layers provide control over electric and mechanical properties (conductivity, emissivity, mechanical robustness) and seal rings help to insulate and prevent loss within a device. C2 teaches further comprising forming a first metallization layer (Figure 1F-1H, redistribution structure 600 contains conductive layers 604 with through vias 606 which make up at least a first metallization layer). C2 does not expressly indicate the use of seal rings. Pan teaches forming a seal ring portion (Figures 2, 6; seal ring 110′) over a passivation layer in the same processing step of the same material (“top surface of the second conductive features and the second portion of the seal ring are substantially level”). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 1 above under the teachings of C2 and Pan to form a metallization layer with a seal ring after forming the facet recess. This may be accomplished using methods (deposition) and materials (conductive materials like metals) known in the art, and would predictably result in a device where electrical components that rely on conductivity between device layers are efficiently operable due to the metallization of intermediate layers. Regarding claim 18: C1 in view of Shi, and further in view of C2 discloses optical device of claim 17. C1 does not disclose the seal ring as claimed. Pan teaches forming a seal ring portion (Figures 2, 6; seal ring 110′) over a passivation layer in the same processing step of the same material (“top surface of the second conductive features and the second portion of the seal ring are substantially level”). This constitutes the first redistribution layer comprises a seal ring. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 15 above under the teachings of Pan to form a seal ring as in Pan concurrently with the formation of the redistribution conductive layers 604 of C2, because Pan expressly teaches that this approach uses the same mask, deposition, and patterning steps of the redistribution layer itself: “Next in FIG. 3, a passivation layer 116 is formed over conductive features 114 , seal rings 110 , and passivation layer 112 . In various embodiments, passivation layer 116 may be formed using a similar material and/or similar processes as described above with regards to passivation layer 112 ,” Pan, Col. 6 ln 35-50. Regarding claim 19: C1 in view of Shi, and further in view of C2 and Pan discloses optical device of claim 18, wherein the first redistribution layer comprises a dummy portion. any portion of the redistribution layer which does not engage in electrical function can be said to be a ‘dummy portion’ . 07-21-aia AIA Claim (s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11404404 B2, hereafter C1) in view of Chen (US 11372160 B2, hereafter C2), and further in view of Shi (US 9787054 B2) and Andry (US 8855452 B2) . Regarding claim 7: C1 in view of C2 and further in view of Shi teaches the method of claim 6. C1 is silent on the use of a lens and its alignment with the grating coupler. However, in optical devices, the use of lenses to direct, modify, (de)collimate, etc. light is ubiquitous and aligning a lens with a coupler is one of the foremost considerations for a skilled artisan. Failure to align a lens means optical signal is lost. Andry discloses photonic chip optical coupling structures (Title), wherein: A substrate (substrate 106, Figure 1) comprises a first lens (112) aligned with the grating coupler (122). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 6 above under the teachings of Andry to include a first lens that is aligned with the grating coupler that is the optical device 113 as taught in C1. This may be accomplished using materials, components (substrate, lens, grating structure), machining techniques (etching for creating space for components, deposition for layers themselves), and placement oversight known to a skilled artisan. Predictably, this would result in a device which benefits from being able to direct optical signals from external sources (i.e. a fiber, a waveguide, a laser, etc.) into the device with minimal loss . 07-21-aia AIA Claim (s) 8, 9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11372160 B2, hereafter C2) in view of Shi (US 9787054 B2) . Regarding claim 8: C2 discloses a method of manufacturing an optical device (Title, Figures 1A-1K), the method comprising: removing a first portion of a metallization layer over first optical components to form a first opening; Figure 1G shows a portion of redistribution structure 600 over waveguides 140 as being a set of ‘first optical components’ which are removed by anisotropic etching to expose the underlying semiconductor substrate 110, forming a first opening (Specification, col. 9, second paragraph, “Referring to Fig. 1G…”). To the extent that the claim requires the opening to be formed before bonding, this is a rearrangement of process steps. A skilled artisan would recognize the etch step as relocatable in the process flow to suit dielectric/encapsulant choice – rearrangement of order of process steps is prima facie obvious. depositing a first gap fill material into the first opening; Specification, col. 14, ln. 1-17 states that a notch N (gap) is filled with a dielectric material (first material). bonding a first semiconductor device to the metallization layer; Figure 1B, IC die 200 is bonded to interconnection structure 150 (metallization layer) of the semiconductor wafer via bonding pads 238 to through vias 160. depositing a second gap fill material around the first semiconductor device; Figure 1C, encapsulant 300 is formed on the semiconductor wafer to laterally encapsulate electric die 200, the material of the encapsulant being silicon oxide/nitride, FSG, a low-k material, or other known moulding compound (“a material of the encapsulant 300 includes silicon oxide, silicon nitride, silicon carbide, fluoride-doped silicate glass (FSG), low-k dielectric, or the like”) bonding a support substrate to the second gap fill material; Figure 1D, bonding layer 400 and supporting substrate 500 formed over second surface 200b of IC die 200 [first semiconductor device] and top surface 300a of encapsulant 300 depict fusion bonding between second gap fill and support substrate. after the bonding the support substrate, removing portions of the first gap fill material and the second gap fill material to form a first facet; Figure 1G, after the supporting substrate 500 is bonded and structure is flipped/thinned, a portion of substrate 110 (first gap fill region) is removed to form notch N; the etched sidewall and adjacent encapsulant face define the facet. C2 does not teach a spacer as claimed. Shi teaches an optical package (Title), wherein: Shi teaches a first spacer (i.e. spacer 330). Shi further teaches a family of materials used for the spacer (“A silica spacer [or isolator] 330 may be bonded…”; “the spacer may include a silica spacer, a glass spacer, a polymer spacer, a polyimide spacer, an epoxy spacer, or a resin spacer.”) Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in C2 under the teachings of Shi to include a spacer element along the sidewall of the first facet. This may be accomplished using methods (ordinary placement of parts) and materials (spacer materials as disclosed) known to a skilled artisan, and would predictably result in a device with a spacer used to provide precise mechanical placement for structural integrity and control over the electric properties of the invention. Regarding claim 9: C2 in view of Shi discloses the invention of claim 8, further comprising: forming a first redistribution layer connected to the metallization layer after the forming the first spacer. Figure 1F, 1H, redistribution structure 600 with redistribution conductive layers 604 connected to through vias 160 and thus to interconnection structure 150 [this constitutes a metallization layer]. To the extent that the claim requires the redistribution layer formation to precede the spacer formation, this process is a simple reordering of steps. A skilled artisan would recognize the redistribution layer formation as relocatable in the process flow to suit dielectric/spacer selection choice – rearrangement of order of process steps is prima facie obvious. Regarding claim 14: C2 in view of Shi discloses the invention of claim 8, further comprising: attaching a fiber unit aligned with an edge coupler through the first spacer (optical fiber F, aligned to and optically coupled with edge-coupler waveguide 140). Insofar as the claim requires the fiber unit to be a fiber array unit (that is, an array of fibers with N fibers), the fiber unit of C2 meets the limitation where the fiber array is an array with N = 1 . 07-21-aia AIA Claim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11372160 B2, hereafter C2) in view of Shi (US 9787054 B2), and further in view of Pan (US9780046B2) . Regarding claim 10: C2 in view of Shi discloses the invention of claim 9. C2 does not teach the seal ring as claimed, but seal rings are a well-known feature of semiconductor packaging layers used to prevent crack propagation and moisture ingress; they are an obvious and well understood/known design choice in packaging. Pan teaches forming a seal ring portion (Figures 2, 6; seal ring 110′) over a passivation layer in the same processing step of the same material (“top surface of the second conductive features and the second portion of the seal ring are substantially level”). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 9 above under the teachings of Pan to form a seal ring as in Pan concurrently with the formation of the redistribution conductive layers 604 of C2, because Pan expressly teaches that this approach uses the same mask, deposition, and patterning steps of the redistribution layer itself: “Next in FIG. 3, a passivation layer 116 is formed over conductive features 114 , seal rings 110 , and passivation layer 112 . In various embodiments, passivation layer 116 may be formed using a similar material and/or similar processes as described above with regards to passivation layer 112 ,” Pan, Col. 6 ln 35-50. Regarding claim 11: C2 in view of Shi discloses the invention of claim 10, wherein the forming the first redistribution layer forms a dummy portion. any portion of the redistribution layer which does not engage in electrical function can be said to be a ‘dummy portion’ . 07-21-aia AIA Claim (s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11372160 B2, hereafter C2) in view of Shi (US 9787054 B2) and Andry (US 8855452 B2) . Regarding claim 12: C2 in view of Shi discloses the invention of claim 11. C2 does not disclose the dummy portion’s position or function as claimed. Andry discloses photonic chip optical coupling structures (Title), wherein: a dummy portion (Figure 1, reflective structure 124) is located to reflect light to a grating coupler (122) within a set of first optical components. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 11 above under the teachings of Andry, to configure the dummy portion to be reflective and positioned such that it reflects light into a grating coupler. This may be accomplished using materials, machining and placement methods known in the art, and would predictably result in a device which additionally contains optically active and optically functional components for the transmission of light, with placement that maximizes coupling efficiency. Regarding claim 13: C2 in view of Shi discloses the invention of claim 12. C2 is silent on the use of a lens and its alignment with the grating coupler. However, in optical devices, the use of lenses to direct, modify, (de)collimate, etc. light is ubiquitous and aligning a lens with a coupler is one of the foremost considerations for a skilled artisan. Failure to align a lens means optical signal is lost. Andry discloses photonic chip optical coupling structures (Title), wherein: A substrate (substrate 106, Figure 1) comprises a first lens (112) aligned with the grating coupler (122). Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 6 above under the teachings of Andry to include a first lens that is aligned with the grating coupler 122 of Andry. This may be accomplished using materials, components (substrate, lens, grating structure), machining techniques (etching for creating space for components, deposition for layers themselves), and placement oversight known to a skilled artisan. Predictably, this would result in a device which benefits from being able to direct optical signals from external sources (i.e. a fiber, a waveguide, a laser, etc.) into the device with minimal loss . 07-21-aia AIA Claim (s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11404404 B2, hereafter C1) in view of Shi (US 9787054 B2) . Regarding claim 15: C1 discloses an optical device (semiconductor with photonics die, Title) comprising: a first semiconductor device (electronics die ED, comprising substrate 121, devices 122, interconnect 123 with bonding pads 123c, Figures 1a, and 1f) bonded to an optical interposer (photonics wafer PW, Figure 1A, 1F); a support substrate bonded to the first semiconductor device (supporting substrate 210, 310 is disposed over insulating material 130A above the ED, opposite PD, as shown in Figures 4A/B and 6), wherein a sidewall (Figure 1F, sidewall SW1) of the optical interposer is offset from a sidewall (SW2) of the support substrate (Figure 1F, top portion 1112 of substrate 111 is offset from bottom portion 1111, where supporting substrate 210/310 overhand the sidewall SW1); C1 does not teach the spacer lining as claimed. The use of spacers is well established and a ubiquitous practice in the art. A skilled artisan would find it obvious to use a spacer lining for mechanical separation and electrodynamic control. Shi teaches an optical device (Title), further comprising: a first spacer lining (Figure 1, spacer 130) the sidewall of the optical interposer. The spacer 130 is bonded to an optical interposer, the Si PIC. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the invention of C1 under the teachings of Shi, to include a spacer lining for the optical interposer. The facet sidewalls SW1 and SW2 of C1 leave the edge-coupling facet (SW1) exposed, and Shi teaches that bonding a spacer to the edge coupler facet allows for controlled mode-size expansion, suppressing return loss and providing a defined, protected coupling interface. This could be accomplished using bonding and layer deposition techniques known to a skilled artisan, and would predictably result in a device where coupling efficiency is improved and return loss is decreased at the interposers optical edge. Regarding claim 16: C1 in view of Shi discloses optical device of claim 15. wherein after the forming the facet recess the first optical interposer comprises an edge coupler adjacent to the sidewall of the first facet recess (claim 4, Figure 1F; edge coupler 113 is adjacent to sidewall SW1 formed from facet 1111f). C1 does not teach a spacer as claimed. Shi teaches an optical device (Title), further comprising: a first spacer lining (Figure 1, spacer 130) the sidewall of the optical interposer. The spacer 130 is bonded to an optical interposer, the Si PIC. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 15 above under the teachings of Shi to include a spacer bonded to the optical interposer. This may be accomplished using components/methods (deposition, placement of pre-formed components, bonding between components), materials (i.e. Si based substrates), and design oversight known to a skilled artisan, and would predictably result in a device which benefits from the electromechanical properties of a spacer element, reducing the optical/electrical crosstalk during device operation and improving signal integrity . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 11404404 B2, hereafter C1) in view of Shi (US 9787054 B2), and further in view of Chen (US 11372160 B2, hereafter C2), Pan (US9780046B2), and Andry (US 8855452 B2) . Regarding claim 20: C1 in view of C2, and further in view of Pan discloses optical device of claim 19. C1 is silent on the use of a lens and its alignment with the grating coupler. However, in optical devices, the use of lenses to direct, modify, (de)collimate, etc. light is ubiquitous and aligning a lens with a coupler is one of the foremost considerations for a skilled artisan. Failure to align a lens means optical signal is lost. Andry discloses photonic chip optical coupling structures (Title), wherein: A substrate (substrate 106, Figure 1) comprises a first lens (112) aligned with the grating coupler (122) within the optical interposer. Before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to modify the invention described in the rejection of claim 19 above under the teachings of Andry to include a first lens that is aligned with the grating coupler that is the optical device 113 as taught in C1. This may be accomplished using materials, components (substrate, lens, grating structure), machining techniques (etching for creating space for components, deposition for layers themselves), and placement oversight known to a skilled artisan. Predictably, this would result in a device which benefits from being able to direct optical signals from external sources (i.e. a fiber, a waveguide, a laser, etc.) into the device with minimal loss. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PREET B PATEL whose telephone number is (571)272-2579. The examiner can normally be reached Mon-Thu: 8 am - 6 pm PST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS A HOLLWEG can be reached at 571-270-1739 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PREET B PATEL/Examiner, Art Unit 2874 /THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874 Application/Control Number: 18/627,789 Page 2 Art Unit: 2874 Application/Control Number: 18/627,789 Page 3 Art Unit: 2874 Application/Control Number: 18/627,789 Page 4 Art Unit: 2874 Application/Control Number: 18/627,789 Page 5 Art Unit: 2874 Application/Control Number: 18/627,789 Page 6 Art Unit: 2874 Application/Control Number: 18/627,789 Page 7 Art Unit: 2874 Application/Control Number: 18/627,789 Page 8 Art Unit: 2874 Application/Control Number: 18/627,789 Page 9 Art Unit: 2874 Application/Control Number: 18/627,789 Page 10 Art Unit: 2874 Application/Control Number: 18/627,789 Page 11 Art Unit: 2874 Application/Control Number: 18/627,789 Page 12 Art Unit: 2874 Application/Control Number: 18/627,789 Page 13 Art Unit: 2874 Application/Control Number: 18/627,789 Page 14 Art Unit: 2874 Application/Control Number: 18/627,789 Page 15 Art Unit: 2874 Application/Control Number: 18/627,789 Page 16 Art Unit: 2874 Application/Control Number: 18/627,789 Page 17 Art Unit: 2874 Application/Control Number: 18/627,789 Page 18 Art Unit: 2874 Application/Control Number: 18/627,789 Page 19 Art Unit: 2874 Application/Control Number: 18/627,789 Page 20 Art Unit: 2874 Application/Control Number: 18/627,789 Page 21 Art Unit: 2874 Application/Control Number: 18/627,789 Page 22 Art Unit: 2874 Application/Control Number: 18/627,789 Page 23 Art Unit: 2874 Application/Control Number: 18/627,789 Page 24 Art Unit: 2874 Application/Control Number: 18/627,789 Page 25 Art Unit: 2874 Application/Control Number: 18/627,789 Page 26 Art Unit: 2874 Application/Control Number: 18/627,789 Page 27 Art Unit: 2874 Application/Control Number: 18/627,789 Page 28 Art Unit: 2874 Application/Control Number: 18/627,789 Page 29 Art Unit: 2874
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