DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-19, 21-24, 26, 28-34 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wu et al (US 2022/0310452 A1; hereinafter “Wu”)
In regard to claim 16, Wu teaches a semiconductor device (semiconductor device 200) (Fig. 14 and paragraph 11), comprising:
a multi-gate structure (a plurality of metal gate structures 250) over a semiconductor substrate (substrate 202 includes another single crystalline semiconductor) including a top inner gate portion (the top inner metal gate electrodes 254 of the metal gate structures 250 in annotated Fig. 14 below) (Fig. 13, annotated Fig. 14 and paragraphs 13 and 31);
a source/drain feature (S/D features 240) located laterally adjacent to the multi-gate structure (Fig. 14 and paragraph 22);
an interlayer dielectric layer (ILD layers 256) over the multi-gate structure and the source/drain feature (Fig. 14 and paragraph 33);
a source/drain contact (contacts/vias 260) extending through the interlayer dielectric layer to the source/drain feature (the contacts/vias 260 are shown extending through the ILD layers 256 in Fig. 14) (Fig. 14 and paragraph 33); and
a side liner (gate spacers 222) on the source/drain contact extending to a lowest edge in contact with the source/drain feature (the gate spacer 222 is shown extending to the bottom edge of the contacts/vias 260 contacting the S/D features 240 in Fig. 14) (Fig. 14 and paragraph 19), wherein the lowest edge is located above the top inner gate portion (the lowest edge of the gate spacer 222 is shown above the top inner metal gate electrodes 254 of the metal gate structures 250 in annotated Fig. 14 below) (Fig. 13, annotated Fig. 14 and paragraph 31).
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In regard to claim 17, Wu teaches wherein:
the top inner gate portion has an uppermost surface (the upper most surface of the top inner metal gate electrodes 254 of the metal gate structures 250 is shown in annotated Fig. 14 above); and the lowest edge is located above the uppermost surface of the top inner gate portion (the lowest edge of the gate spacers 222 is shown above the uppermost surface of the metal gate electrodes 254 in annotated Fig. 14 above).
In regard to claim 18, Wu teaches wherein:
the multi-gate structure has an outer gate portion above the top inner gate portion (the metal gate electrodes 254 of the metal gate structures 250 above the top inner metal gate electrodes 254 shown in annotated Fig. 14 above), wherein the outer gate portion has an uppermost surface distanced from the uppermost surface of the top inner gate portion (the uppermost surface of metal gate structure 250 above the top inner metal gate electrodes 254 is shown distanced from the uppermost surface of the top inner metal gate electrodes 254 in annotated Fig. 14 above); and
the lowest edge of the side liner is located below the uppermost surface of the multi- gate structure (the lowest edge of the gate spacers 222 is shown below the uppermost edge of the uppermost surface of metal gate electrodes 254 that function as the outer gate portions as shown in Fig. 14).
In regard to claim 19, Wu teaches wherein the side liner is a silicon nitride redistribution (SNR) layer (the gate spacers 222 includes SiN and functions as a silicon nitride redistribution (SNR) layer) (Fig. 14 and paragraph 21). Further the examiner notes intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, and then it meets the claim. Ex Parte Masham, 2 USPQ F.2d 1647 (1987)).
In regard to claim 21, Wu teaches a semiconductor device (semiconductor device 200) (Fig. 14 and paragraph 11), comprising:
a multi-gate structure (a plurality of metal gate structures 250) (Fig. 14 and paragraphs 13 and 31);
a source/drain feature (S/D features 240) laterally adjacent to the multi-gate structure (Fig. 14 and paragraph 22); and
an isolation layer (an isolation layer 226) below the source/drain feature (Fig. 14 and paragraph 21), the isolation layer comprising a dielectric material having a band gap of at least 4 eV (the isolation layer 226 includes an isolation material such as SiO, SiN, or aluminum oxide (Al2O3) which are known to have a band gap greater than 4eV) (Fig. 14 and paragraph 21).
In regard to claim 22, Wu teaches wherein the dielectric material has a band gap of from 4 eV to 8.9 eV (the bandgap of SiO is known amongst those skilled in the art to have a band gap between 4 eV to 8.9 eV) (paragraph 21).
In regard to claim 23, Wu teaches wherein the isolation layer has a dielectric constant of less than ten (as the dielectric constant is material dependent, the isolation layer 226 includes an isolation material such as SiO would have a dielectric constant of less than 10) (paragraph 21).
In regard to claim 24, Wu teaches wherein the dielectric material comprises silicon oxide, silicon nitride, or a combination thereof (the isolation layer 226 includes an isolation material such as Silicon Oxide (SiO) or Silicon Nitride (SiN)) (paragraph 21).
In regard to claim 26, Wu teaches wherein the isolation layer extends from the multi-gate structure to an adjacent multi-gate structure (the isolation layer 226 is shown extending from one multi-gate structure to another in Fig. 14).
In regard to claim 28, Wu teaches wherein the multi-gate structure surrounds a plurality of vertically spaced nanosheet channels (a plurality of metal gate structures 250 are shown surrounding the channels of semiconductor layer 210A in Fig. 14).
In regard to claim 29, Wu teaches a semiconductor device (semiconductor device 200) (Fig. 14 and paragraph 11), comprising:
a first nanosheet channel and a second nanosheet channel (a first and second semiconductor layer 210A annotated as 1st and 2nd are shown in annotated Fig. 14 below) (annotated Fig. 14 and paragraphs 9-10), the second nanosheet channel vertically spaced above the first nanosheet channel and being an uppermost nanosheet channel (the semiconductor layer 210A annotated as 2nd is shown spaced apart and above the semiconductor layer 210A annotated as 1st in annotated Fig. 14 below);
a gate structure surrounding the first nanosheet channel and the second nanosheet channel (as a dummy gate structure 220 is replaced with metal gate structures 250, the metal gate structures 250 surrounds the semiconductor layers 210 as shown in Fig. 2) (Fig. 2 and paragraph 29), the gate structure including an outer gate portion above the second nanosheet channel (a metal gate structure 250 annotated as OG function as an outer gate portion) (annotated Fig. 14), a first inner gate portion below the first nanosheet channel, and a second inner gate portion below the second nanosheet channel (metal gate electrodes 254 of the metal gate structures 250 are shown below the semiconductor layers 210A annotated as 2nd and 1st as shown in annotated Fig. 14 below);
a first inner spacer surrounding the first inner gate portion and a second inner spacer surrounding the second inner gate portion (gate dielectric layers 252 are shown surrounding the metal gate electrodes 254 below the semiconductor layer 210A annotated as 2nd and 1st) (annotated Fig. 14 and paragraph 31); and
a source/drain feature (S/D features 240) laterally adjacent to the gate structure and separated from the first inner gate portion by the first inner spacer and from the second inner gate portion by the second inner spacer (the S/D features 240 are shown spaced apart from the metal gate electrodes 254 by the gate dielectric layers 252 in Fig. 14).
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In regard to claim 30, Wu teaches the semiconductor device, further comprising a source/drain contact (contacts/vias 260) extending to the source/drain feature and a side liner (gate spacers 222) on the source/drain contact (Fig. 13, Fig. 14, paragraphs 19 and 33), the side liner extending to a lowest edge located above the second inner gate portion (the gate spacers 222 are shown extending to the metal gate structures 250 in annotated Fig. 14 above).
In regard to claim 31, Wu teaches wherein the lowest edge of the side liner is located below an uppermost surface of the outer gate portion (the lowest edge of the gate spacers 222 is shown below the uppermost edge of the uppermost surface of metal gate electrodes 254 that functions as the outer gate portions as shown in Fig. 14).
In regard to claim 32 Wu teaches, wherein the lowest edge of the side liner is located at or above an uppermost surface of the second nanosheet channel (the lowest edge of the gate spacers 222 is shown above the annotated second nanosheet channel in annotated Fig. 14 above).
In regard to claim 33, Wu teaches wherein the side liner is a silicon nitride redistribution layer (the gate spacer 222 includes SiN and functions as a silicon redistribution (SNR) layer) (Fig. 14 and paragraph 21). Further the examiner notes intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, and then it meets the claim. Ex Parte Masham, 2 USPQ F.2d 1647 (1987))
In regard to claim 34, Wu teaches an isolation layer (an isolation layer 226) below the source/drain feature, the isolation layer comprising a dielectric material (the isolation layer 226 includes an isolation material such as SiO, SiN, aluminum oxide (Al2O3)) (Fig. 14 and paragraph 21).
Claim 21 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen et al. (US 2022/0285510 A1; hereinafter “Chen”).
In regard to claim 21, Chen teaches a semiconductor device (CMOS device 100) (Fig. 13 and paragraph 14), comprising:
a multi-gate structure (a multi-gate structure is shown in gate structures 250) (Fig. 13 and paragraph 21);
a source/drain feature (epitaxial source/drain features 500B) laterally adjacent to the multi-gate structure (Fig. 13 and paragraph 15); and
an isolation layer (isolation features 550) below the source/drain feature (Fig. 13 and paragraph 34), the isolation layer comprising a dielectric material having a band gap of at least 4 eV (isolation features 550 may be silicon nitride which is known to have a bandgap of at least 4eV).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 16 above, and further in view of Liaw ( US 2021/0313333 A1) and Yu et al. (US 2023/0062026 A1; hereinafter “Yu”).
In regard to claim 20, Wu teaches wherein: the multi-gate structure has an outer gate portion above the top inner gate portion (the metal gate electrodes 254 of the metal gate structures 250 above the top inner metal gate electrodes 254 shown in annotated Fig. 14 above);
a top nanosheet (a top semiconductor layer 210A) separates the outer gate portion from the top inner gate portion (Fig. 14 and paragraph 14).
However, Wu doesn’t explicitly teach the outer gate portion has a vertical thickness of from 5 to 30 nanometers; the top nanosheet has a vertical thickness of from 3 to 15 nanometers; and the top inner gate portion has a vertical thickness of from 3 to 15 nanometers.
Liaw teaches a multi-gate structure (an SRAM cell 400) over a semiconductor substrate (a substrate 412 having various doped regions) (Fig. 3C and paragraph 53), wherein:
an outer gate portion (a gate electrode 430B) has a vertical thickness of from 5 to 30 nanometers (the gate electrodes 430B of SRAM cell 400 may include a TiN layer with a thickness of about 4 nm to about 30 nm) (Fig. 3D and paragraph 56).
It would’ve been obvious to one skilled in the art to combine the teachings of Wu with the teachings of Liaw to have the outer gate portion have a vertical thickness of from 5 to 30 nanometers since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Note that the specification contains no disclosure of either the critical nature of the claimed vertical thickness of the outer gate portion or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen vertical thickness of the outer gate portion or upon another variable recited in a claim, the Applicant must show that the chosen vertical thicknesses of the outer gate portion are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Yu teaches a multi-gate structure (a semiconductor device structure 100) over a semiconductor substrate (substrate 102 may include a single crystalline semiconductor) (Fig. 19 and paragraphs 16), wherein:
a top nanosheet has a vertical thickness of from 3 to 15 nanometers (each first semiconductor layer 106a, 106b has a thickness ranging from about 4 nanometers (nm) to about 10 nm) (Fig. 19 and paragraph 20); and
a top inner gate portion has a vertical thickness of from 3 to 15 nanometers (each second semiconductor layer 108a, 108b has a thickness ranging from about 8 nm to about 15 nm which is removed to form the interfacial layer 159 (not shown), the gate dielectric layer 166, and the second gate electrode layer 186 which all together function as a top inner gate portion) (Fig. 19 and paragraphs 21 and 69).
It would have been obvious to one skilled in the art to combine the teachings of Wu with the teachings of Yu since the specification contains no disclosure of either the critical nature of the claimed vertical thickness of the top nanosheet and top inner gate or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen vertical thickness of the top nanosheet and top inner gate or upon another variable recited in a claim, the Applicant must show that the chosen vertical thickness of the outer gate portion are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 25 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 21 or 34 above, and further in view of Liaw (US 2022/0367659 A1; hereinafter “Liaw659”).
In regard to claim 25, Wu doesn’t explicitly teach wherein the isolation layer is a multi-film structure comprising a plurality sublayers.
In regard to claim 25, Liaw659 teaches a semiconductor device (a GAA device 200) (Fig. 12 and paragraph 23), wherein an isolation layer (an isolation feature 230) is a multi-film structure comprising a plurality of sublayers (the isolation feature 230 may be a multi-layer structure) (Fig. 12 and paragraph 29).
It would’ve been obvious to one skilled in the art to combine the teachings of Wu with the teachings of Liaw659 to have the isolation layer comprise a multi-film structure comprising a plurality of sublayers since this layout allows electrical separation of fins from other active components as taught by Liaw659.
In regard to claim 35, Wu doesn’t explicitly teach wherein the isolation layer is a multi-film structure comprising sublayers.
In regard to claim 35, Liaw659 teaches a semiconductor device (a GAA device 200) (Fig. 12 and paragraph 23), wherein an isolation layer (an isolation feature 230) is a multi-film structure comprising sublayers (the isolation feature 230 may be a multi-layer structure) (Fig. 12 and paragraph 29).
It would’ve been obvious to one skilled in the art to combine the teachings of Wu with the teachings of Liaw659 to have the isolation layer comprise a multi-film structure comprising sublayers since this layout allows electrical separation of fins from other active components as taught by Liaw659.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 21 above, and further in view of Frougier et al. (US 2023/0060619 A1; hereinafter “Frougier”).
In regard to claim 27, Chen doesn’t explicitly teach wherein the source/drain feature is a strained epitaxial feature in contact with the isolation layer.
Frougier teaches a semiconductor device (a semiconductor device as shown in Fig. 31) (Fig. 31 and paragraph 42), wherein a source/drain feature (source-drain material 1610) is a strained epitaxial feature in contact with the isolation layer (a sacrificial layer is replaced with a low-k dielectric material and/or dielectric stressor material which yields strained epitaxial source-drain) (Fig. 31 and paragraphs 103 and 143).
It would’ve been obvious to one skilled in the art to combine the teachings of Chen with the teachings of Frougier to have the source/drain feature be a strained epitaxial feature in contact with the isolation layer since lattice strains enhance charge mobility across device elements as taught by Frougier (paragraph 103).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. (US 2022/0173097 A1)
Yu et al. (US 2023/0075343 A1)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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