DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II which corresponds to claims 1-10 in the reply filed on 7/15/2026 is acknowledged. Claims 11-20 are withdrawn from further consideration, pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Inventions or Species.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/5/2024 and 4/8/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 4-6 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Ohsawa et al. (US-20230309298A1, hereinafter Ohsawa)
Regarding Claim 1.
Ohsawa teaches in Fig.12A-12B and in related text A device, comprising:
an alternating stack of insulating layers (#32) and electrically conductive layers (#46)extending along a first horizontal direction through a first memory array region (#100) and a staircase region (#300), wherein the alternating stack comprises stepped surfaces in the staircase region; (Fig.12A-12B [0048][0136]90155])
vertical stacks of at least one insulating plate (#32) and at least one spacer material plate (#42), wherein each of the vertical stacks is located on a respective horizontal surface segment of the stepped surfaces in the staircase region;([0078-0079] [0136])
a dielectric material portion (#65) located in the staircase region having a stepped bottom surface and contacting each of the vertical stacks (#32/#42);([0085-0086]) and
layer contact via structures (#86) located in the staircase region and vertically extending through the dielectric material portion (#65) and a respective vertical stack of the vertical stacks (#32/#42) and contacting a respective one of the electrically conductive (#46). ([0145-0146])
Regarding Claim 4.
Ohsawa teaches The device of claim 1,
Ohsawa further teaches further comprising a backside trench fill structure (#79/#76/#74) comprising a dielectric backside trench fill material (#74 insulating spacer such as silicon oxide) at least in a peripheral portion of the backside trench fill structure. (Fig.11 [0138-0142])
Regarding Claim 5.
Ohsawa teaches The device of claim 4, wherein:
Ohsawa further teaches the spacer material plates (#42) comprise a dielectric material having a different material composition than the insulating plates and the insulating layers (#32); and
each sidewall of the insulating plates and the spacer material plates is laterally offset from the dielectric backside trench fill structure. ([0078-0079] [0120] [0138-0142] the dielectric material pads 42′ comprise silicon nitride, and the insulating pads 32′ comprise silicon oxide)
Regarding Claim 6.
Ohsawa teaches The device of claim 5,
Ohsawa further teaches wherein:
the spacer material plates (#42) comprise silicon nitride; and
the insulating plates and the insulating layers (#32) comprise silicon oxide ([0078-0079] the dielectric material pads 42′ comprise silicon nitride, and the insulating pads 32′ comprise silicon oxide)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ohsawa et al. (US-20230309298A1, hereinafter Ohsawa), and further in view of Tanaka et al. (US-20220328512-A1, hereinafter Tanaka).
Regarding Claim 2.
Ohsawa teaches The device of claim 1,
Ohsawa does not explicitly disclose further comprising:
a second memory array region that is laterally spaced apart from the first memory array region by a staircase region containing the stepped surfaces;
memory opening fill structures each comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel vertically extending through the alternating stack and located within the first memory array region and the second memory array region.
Tanaka discloses first and second memory array regions #100A and #100B laterally spaced apart by an inter-array region #200 containing staircase structure and retro-stepped dielectric material portions #165/#265 (Figs. 1A-1F [0056][0062][0069]) Tanaka further discloses memory opening fill structures #58 in both memory array regions, each comprising a vertical stack of memory elements and a vertical semiconductor channel #60 extending through the alternating stack (Figs. 11A-11D [0061-0062] [0096] [0129])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Oshawa’s device with the teachings of Tanaka, as identified above, so that the staircase contacts provide electrical access to corresponding conductive layers in both arrays through connecting bridge portions. A reasonable expectation of success would have existed because the modification applies the local terrace/contact arrangement to the corresponding staircase portions of an alternating-layer memory structure while retaining the separate bridge connection.
Regarding Claim 3.
Ohsawa modified by Tanaka teaches The device of claim 2,
Tanaka further disclose wherein: the electrically conductive layers (#146/#246) have a respective bridge region (#240) having a respective strip width within the staircase region (#200); and
the electrically conductive layers have a respective uniform width greater than the strip width in the first memory array region (#100A), the second memory array region (#100B), and portions of the staircase region that are located outside the bridge region. (Figs. 18A-18B [0090] [0161-0164])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Ohsawa and Tanaka with the teachings of Tanaka, as identified above, because this geometry would predictably preserve the conductive connection while leaving Ohsawa’s local pad stacks and through-pad contacts on the adjoining staircase terraces.
Allowable Subject Matter
Claims 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein comprising scale strip stacks of at least one insulating scale strip and at least one metallic strip located on the respective horizontal surface segment of the stepped surfaces in the staircase region and laterally offset from the respective one of the vertical stacks located on the same respective horizontal surface segment of the stepped surfaces. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 8 contain allowable subject matter because they depend from claim 7
Claim 9 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the spacer material plates and the electrically conductive layers comprise a same electrically conductive material; and each sidewall of the insulating plates and the spacer material plates is in direct contact with the dielectric backside trench fill material. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 10 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein a topmost one of the vertical stacks is located above a horizontal plane of a topmost one of the electrically conductive layers in the memory array region. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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