DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 10-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chaung et al. (US 20240071911 A1, hereinafter Chuang)
With regards to claim 1, Chuang discloses a structure (FIG. 1) comprising:
a bottom bonding dielectric layer (bonding dielectric 120) located on a surface of a bottom semiconductor die, (semiconductor substrate 101)
wherein the bottom bonding dielectric layer and the bottom semiconductor die have a bottom portion of an inductor-capacitor (l-C) circuit (at least inductive coil 332/passive device 111) present therein; and
a top bonding dielectric layer (bonding dielectric 220) located on a surface of a top semiconductor die (semiconductor substrate 201) and in contact with the bottom bonding dielectric layer,
wherein the top bonding dielectric layer and the top semiconductor die have a top portion of the L-C circuit (at least inductive coil 333/passive device 211) present therein,
wherein the top portion of the L-C circuit is connected to the bottom portion of the L-C circuit at a hybrid bonding interface. (at least interface 311/321/331, see at least FIG. 1)
With regards to claim 2, Chuang discloses the structure of Claim 1, wherein the hybrid bonding interface is located between the top bonding dielectric layer and the bottom bonding dielectric layer. (see FIG. 1)
With regards to claim 3, Chuang discloses the structure of Claim 1, wherein the hybrid bonding interface connecting the bottom portion of the L-C circuit to the top portion of the L-C circuit includes a metal-to-metal bond and a dielectric-to-dielectric bond. (See FIG. 1, showing the bonding between dielectrics 120/220 and metal to metal 313/312)
With regards to claim 4, Chuang discloses the structure of Claim 1, wherein the top portion of the L-C circuit comprises a top capacitor portion and a top inductor, (at least inductive coil 333/passive device 211) and the bottom portion of the L-C circuit comprises a bottom capacitor portion and a bottom inductor, (at least inductive coil 332 and passive device 111) wherein the top capacitor portion is connected to the bottom capacitor portion at the hybrid bonding interface, and the top inductor is connected to the bottom inductor at the hybrid bonding interface. (See FIG. 1)
With regards to claim 5, Chuang discloses the structure of Claim 4, wherein each the top inductor and the bottom inductor is a planar structure. (See Fig. 1, showing the planar structure)
With regards to claim 6, Chuang discloses the structure of Claim 4, wherein each of the top inductor and the bottom inductor has a shape of a rectangle, a square, a spiral, or a hexagon. (See FIG. 1, showing the rectangle)
With regards to claim 7, Chuang discloses the structure of Claim 4, wherein each of the top capacitor portion and the bottom capacitor portion has a shape of a rectangle, a square, or a circle. (See FIG. 1, showing the rectangle)
With regards to claim 10, Chuang discloses the structure of Claim 1, further comprising a pair of through via structures (at least vias 314/315) present in the top semiconductor die and interconnected to the L-C circuit, wherein one of the through via structures of the pair of through via structures is configurated to allow a signal into the L-C circuit, and the other of the through via structures of the pair of through via structures is configurated to accept the signal that exists the L-C circuit. (See FIG. 1)
With regards to claim 11, Chuang discloses a structure (FIG. 1) comprising:
a bottom bonding dielectric layer (bonding dielectric 120) located on a surface of a bottom semiconductor die, (semiconductor substrate 101)
wherein the bottom bonding dielectric layer has a bottom capacitor portion (at least passive device 111) present therein and the bottom semiconductor die has a bottom inductor (at least inductive coil 332) present therein;
a top bonding dielectric layer (bonding dielectric 220) located on a surface of a top semiconductor die (semiconductor substrate 201) and in contact with the bottom bonding dielectric layer,
wherein the top bonding dielectric layer has a top capacitor portion (at least passive device 211) present therein and the top semiconductor die has a top inductor (at least inductive coil 333) present therein; and
a hybrid bonding interface (at least interface 311/321/331, see at least FIG. 1) located between the bottom bonding dielectric layer and the top bonding dielectric layer at which the top inductor is connected to the bottom inductor, and the top capacitor portion is connected to the bottom capacitor portion. (see Fig. 1, showing the connection)
With regards to claim 12, Chuang discloses the structure of Claim 11, wherein the hybrid bonding interface is located between the top bonding dielectric layer and the bottom bonding dielectric layer. (see Fig. 1, showing the connection)
With regards to claim 13, Chuang discloses the structure of Claim 11, wherein the hybrid bonding interface that connects the top inductor to the bottom inductor includes a dielectric-to-dielectric bond. (See FIG. 1, showing the bonding between dielectrics 120/220 and metal to metal 313/312)
With regards to claim 14, Chuang discloses the structure of Claim 11, wherein the hybrid bonding interface that connects the top capacitor portion to the bottom capacitor portion includes a combination of a dielectric-to-dielectric bond and a metal-to-metal bond. (See FIG. 1, showing the bonding between dielectrics 120/220 and metal to metal 313/312)
With regards to claim 15, Chuang discloses the structure of Claim 11, wherein each of the top inductor and the bottom inductor has a shape of a rectangle, a square, a spiral, or a hexagon. (See FIG. 1, showing the rectangle)
With regards to claim 16, Chuang discloses the structure of Claim 11, wherein each of the top capacitor portion and the bottom capacitor portion has a shape of a rectangle, a square, or a circle. (See FIG. 1, showing the rectangle)
Allowable Subject Matter
Claims 8-9 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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