CTNF 18/628,059 CTNF 85873 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA 2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. 07-21-aia AIA 3. Claim (s) 1, 15-17 , is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al., US 2019/0214344 A1, in view of Kim et al., US 2020/0161236 A1 . Claim 1. Yu et al., disclose a device structure (such as the one in fig. 8A), comprising: -a semiconductor device comprising at least one electrical node (this limitation would read through [0080] wherein is disclosed for example, the dielectric layer stack including the lower-level dielectric layers 760 functions as a matrix for lower metal interconnect structures 780 that provide electrical wiring among the various nodes of the semiconductor devices); -a contact-level dielectric layer (items 662/664/682) overlying the semiconductor device; -a contact via structure (item 782) vertically extending through a lower portion of the contact-level dielectric layer and contacting one of the at least one electrical node; -a metal line structure laterally extending along a first horizontal direction and embedded within an upper portion of the contact-level dielectric layer, wherein the metal line structure comprises a horizontally-extending metal line portion and a downward-protruding pillar portion that protrudes downward below a bottom surface of the horizontally-extending metal line portion and contacts a first segment of a top surface of the contact via structure (this limitation would read through [0080] wherein is disclosed for example, dielectric layer stack including the lower level dielectric layers 760 functions as a matrix for lower metal interconnect structures 780 that provide electrical wiring among the various nodes of the semiconductor devices and landing pads for through-stack contact via structures to be subsequently formed. The lower metal interconnect structures 780 are embedded within the dielectric layer stack of the lower-level dielectric layers 760). However, Yu does not teach “an insulating spacer which contacts a sidewall of the downward-protruding pillar portion and second segment of the top surface of the contact via structure”. In view of Kim et al., US 2020/0161236 A1, fig. 6, [0029], wherein is disclosed “a spacer material 24a is provided on a sidewall of the hard-mask material 24 on the vertical pillar 26. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnect structure of Yu et al., with the feature as taught by Kim et al., because in semiconductor packaging, a sidewall insulating spacer is often placed on the vertical surfaces of a pillar (such as a through-silicon via (TSV) or interposer pillar) to serve several critical functions that improve device performance, reliability, and manufacturability. Further, the spacer can provide mechanical support to the pillar sidewalls, reducing stress concentrations and improving structural integrity. It can also help distribute thermal stress during temperature cycling, which is important in high-reliability packages. Claim 15. Yu et al., disclose the device of Claim 1, wherein: the semiconductor device comprises a field effect transistor; and the electrical node comprises a source region of the field effect transistor, a drain region of the field effect transistor, or a gate electrode of the field effect transistor (this limitation would read through [0047] wherein is disclosed for example, the semiconductor devices 710 can include, for example, field effect transistors including respective transistor active regions 742 (i.e., source regions and drain regions), channel regions 746 and gate structures 750. Claim 16. Yu et al., disclose the device of Claim 15, wherein: the first horizontal direction is a lateral separation direction between the source region and the drain region; the electrical node comprises the drain region; and the metal line structure comprises a drain metal line structure that has an areal overlap with the source region and with the gate electrode in a plan view (this limitation would read through [0047] wherein is disclosed for example, a first element is located “directly above” a second element if the first element is located above a horizontal plane including a topmost surface of the second element and an area of the first element and an area of the second element has an areal overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate semiconductor layer 9)). Claim 17. Yu et al., disclose the device of Claim 15, wherein: the first horizontal direction is a lateral separation direction between the source region and the drain region; the electrical node comprises the gate electrode; and the metal line structure comprises a gate metal line structure that has an areal overlap with the drain region in a plan view, and does not have an areal overlap with the source region in the plan view (this limitation would read through [0047] wherein is disclosed for example, a first element is located “directly above” a second element if the first element is located above a horizontal plane including a topmost surface of the second element and an area of the first element and an area of the second element has an areal overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate semiconductor layer 9)) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 4. Claim s 2-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (A) Claims 2-3, contain allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a bottom periphery of the downward-protruding pillar portion is laterally offset inward from a periphery of the top surface of the contact via structure, and a bottom periphery of the insulating spacer is vertically coincident with the periphery of the top surface of the contact via structure. (B) Claim 4, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein a first segment of the horizontally-extending metal line portion that overlies the contact via structure and is connected to the downward-protruding pillar portion is wider along the second horizontal direction that is perpendicular to the first horizontal direction than remaining second segments of the horizontally-extending metal line portion that do not overlie the contact via structure and are not connected to the downward-protruding pillar portion; and the downward-protruding pillar portion is laterally surrounded by a tubular portion of the insulating spacer. (C) Claims 5-14, are also allowable subject matter, as depend on claim 4. 12-151-07 AIA 07-97 12-51-07 5. Claim s 18-20 are allowed. Reasons for Allowance 6. The following is an examiner's statement of reasons for allowance: 7. Regarding claims 18-20, the prior art failed to disclose or reasonably suggest forming a contact via structure vertically extending through the contact-level dielectric layer and contacting the electrical node; vertically recessing an upper portion of the contact via structure, wherein a recessed top surface of the contact via structure is formed within a first horizontal plane, and a recess cavity is formed above the contact via structure; forming an insulating spacer in a peripheral portion of the recess cavity; forming a line cavity in an upper portion of the contact-level dielectric layer by forming a patterned etch mask layer over the contact-level dielectric layer and by performing an anisotropic etch process, wherein a portion of the recess cavity that is not filled within the insulating spacer is incorporated into the line cavity; and forming a metal line structure in the line cavity directly on the recessed top surface of the contact via structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/628,059 Page 2 Art Unit: 2899 Application/Control Number: 18/628,059 Page 3 Art Unit: 2899 Application/Control Number: 18/628,059 Page 4 Art Unit: 2899 Application/Control Number: 18/628,059 Page 5 Art Unit: 2899 Application/Control Number: 18/628,059 Page 6 Art Unit: 2899 Application/Control Number: 18/628,059 Page 7 Art Unit: 2899
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