DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 02/12/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden to examine both species. This is not found persuasive because claim 20 is independent and comprises distinguished limitations of cease clearing the multiple usage-based disturbance counters during the self-refresh mode, and after cessation of the clearing of the multiple usage-based disturbance counters, refresh at least one row of the multiple rows before existing the self-refresh mode as shows in Fig. 9 as another embodiment.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15 and 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Benedict et al. (US Pub. 2024/0119985).
Regarding claims 1 and 18, Fig. 1 of Benedict discloses an apparatus comprising:
a memory device comprising:
a memory array comprising multiple rows [102, 104, 106, 112, 110, 108, 114, 116];
multiple usage-based disturbance counters [CTRA-2, CTRA-4, CTRA-6, CTRB-12, CTRA-10, CTRA-8, CTRA-8, CTRA-14, and CTRA-16] associated with the memory array; and
logic [Memory Refresh Engine (132) and Row Hammer Disturbance Mitigation Engine (130)] coupled to the memory array and the multiple usage-based disturbance counters, the logic configured to:
perform a refresh operation on a row of the multiple rows responsive to at least one refresh command [paragraphs 041 and 0052 disclose perform refreshing operation base on refresh command when disturbance row detected]; and
clear [reset, as discloses in paragraph 0060, when the number or access for a particular row exceeds a threshold, a refresh operation will perform for that row, and the counter will reset (set back to zero or initial state, which his equivalent to clear) for that particular row] a usage-based disturbance counter of the multiple usage- based disturbance counters responsive to the at least one refresh command [Reset command 302 in Fig. 3], the usage-based disturbance counter configured to store a quantity of accesses to the row of the multiple rows [paragraph 0034 discloses counters store number of access for reach row].
Regarding claim 2, Fig. 1 of Benedict discloses wherein: each respective usage-based disturbance counter of the multiple usage-based disturbance counters [CTRA-2, CTRA-4, CTRA-6, CTRB-12, CTRA-10, CTRA-8, CTRA-8, CTRA-14, and CTRA-16] corresponds to a respective row of the multiple rows of the memory array [102, 104, 106, 112, 110, 108, 114, 116];
Regarding claim 3, Fig. 1 of Benedict discloses wherein: the multiple usage-based disturbance counters [CTRA-2, CTRA-4, CTRA-6, CTRB-12, CTRA-10, CTRA-8, CTRA-8, CTRA-14, and CTRA-16] are integrated with the memory array.
Regarding claim 4, Fig. 1 of Benedict discloses wherein: the memory array comprises multiple word lines; and each respective usage-based disturbance counter [CTRA-2, CTRA-4, CTRA-6, CTRB-12, CTRA-10, CTRA-8, CTRA-8, CTRA-14, and CTRA-16] of the multiple usage-based disturbance counters and each respective row of the multiple rows is coupled to a respective word line of the multiple word lines [102, 104, 106, 112, 110, 108, 114, 116];.
Regarding claim 5, Fig. 1 of Benedict discloses wherein: the refresh operation comprises a self-refresh operation [control by Refresh Engine 132]; and the logic is further configured to generate the at least one refresh command internal [refreshing control signal] to the memory device.
Regarding claim 6, Fig. 1 of Benedict discloses wherein: the refresh operation comprises an auto-refresh operation [refresh operation automatically perform when access number of a row exceed threshold]; and the logic [132] is further configured to receive the at least one refresh command from a source that is external to the memory device [user or host].
Regarding claim 7, Fig. 1 of Benedict discloses wherein the logic [130] is configured to clear the usage-based disturbance counter [reset it to a starting value or zero] responsive to the at least one refresh command by: writing a known value [initial value or zero] into the usage-based disturbance counter.
Regarding claim 8, Fig. 3 of Benedict discloses wherein the logic is further configured to clear the usage-based disturbance counter [resetting] responsive to the at least one refresh command [paragraph 0060] by: writing a zero ("0") into each bit of multiple bits of the usage-based disturbance counter.
Regarding claim 9, Fig. 1 of Benedict discloses wherein the logic is further configured to: perform the refresh operation on two or more rows of the multiple rows responsive to the at least one refresh command [paragraph 0052]; and clear two or more usage-based disturbance counters [counter CTRA-4 and CTRA-6 of the two victim rows 104 and 106] of the multiple usage-based disturbance counters responsive to the at least one refresh command [refresh control signal], each respective usage-based disturbance counter of the two or more usage-based disturbance counters configured to store a respective quantity of accesses to a respective row of the two or more rows [paragraph 0060].
Regarding claim 10, Fig. 10 of Benedict discloses wherein: the memory device further comprises at least one write driver [as discloses in paragraph 0060, a write operation performs. Therefore, a write driver is inherent]; and the at least one write driver is configured to clear substantially simultaneously the two or more usage-based disturbance counters of the multiple usage-based disturbance counters responsive to the at least one refresh command [resetting the counter after writing operation performed].
Regarding claim 11, Fig. 1 of Benedict discloses wherein the logic is further configured to: enter a self-refresh mode [paragraph 0052]; refresh each row of the multiple rows responsive to entry into the self-refresh mode [paragraph 0052]; clear [equivalent to resetting] each usage-based disturbance counter of the multiple usage-based disturbance counters based on refreshing each corresponding row of the multiple rows [as discloses in paragraph 0060, reset the counter after refreshing]; and cease clearing [stop resetting, and count again, similar to steps 602 and 604 in Fig. 7] the multiple usage-based disturbance counters during the self- refresh mode.
Regarding claim 12, Fig. 1 of Benedict discloses wherein the logic is further configured to: refresh at least one row of the multiple rows while in the self-refresh mode [paragraph 0052] after cessation of the clearing [after resetting, the counter can repeat counting and initiate refreshing when the number exceeding the threshold] of the multiple usage-based disturbance counters during the self-refresh mode.
Regarding claim 13, Fig. 1 of Benedict discloses wherein the logic is further configured to: clear each usage-based disturbance counter [reset all counters that has number of accessing exceeding a threshold] corresponding to all rows of the memory array being operated in the self-refresh mode at least once before the cessation [resetting before the counter start counting again] of the clearing of the multiple usage-based disturbance counters during the self-refresh mode.
Regarding claim 14, Fig. 1 of Benedict discloses wherein: the memory device further comprises a refresh address counter configured to store an address of a row targeted for a refresh operation [since each counter stores access number for each for, it indirectly stores information relating to address for reach row]; and the logic is further configured to cease clearing the multiple usage-based disturbance counters during the self-refresh mode based on the refresh address counter [after resetting completed].
Regarding claim 15, Fig. 1 of Benedict discloses wherein the logic is further configured to: cease clearing the multiple usage-based disturbance counters during the self- refresh mode based on the refresh address counter repeating an address value of a row [after a same row got accessed a number of times].
Regarding claim 19, Fig. 1 of Benedict discloses ceasing clearance of the multiple usage-based disturbance counters [the reset is stopped after completed] during a self-refresh mode [no reset operation during refreshing mode], and continue to refresh the multiple rows of the memory array during the self-refresh mode after the ceasing [refreshing operation].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Benedict et al. (US Pub. 2024/0119985) in view of Shore et al. (US Pub. 2020/0251158).
Regarding claim 16, Benedict discloses logic circuit [130] that configured to cease clearing [after it completed resetting] during the multiple usage-based disturbance counters during the self-refresh mode based on the address, but does not specifically disclose a buffer that stores address of the victim or aggressor rows. However, Fig. 3 of Shore discloses a memory device with solutions to row hammer problems having a buffer [350] that stores addresses of victim and aggressor rows [paragraph 0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Shore’s memory device having address buffer to Benedict’s memory having counter for each row such that Benedict’s memory device operates to store the victim and aggressor’s addresses according to Shore’s teachings for the purpose preventing data degradation.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Benedict et al. (US Pub. 2024/0119985) in view of Hyun et al. (US Pub. 2024/0012755).
Regarding claim 17, Benedict discloses all claimed invention, but does not specifically disclose wherein the apparatus comprises a Compute Express Link (CXL) device. However, paragraph 0023 of Hyun discloses a memory device having Compute Express Link (CXL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Hyun’s memory device having CXL to Benedict’s memory having counter for each row such that Benedict’s memory device operates to expand memory storage by allowing dual memory module [paragraph 0040].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825