DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-14, 16-18, 20, and 21 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Haba (US 2021/0407941).
In reference to claim 1, Haba (US 2021/0407941), hereafter “Haba,” discloses a semiconductor package, comprising:
a buffer die 3, paragraph 29;
a first core die stack, 20b in Figure 7A, stacked on the buffer die, the first core die stack including at least one first intermediate core 2a and a first gap filling portion 7a covering an outer surface of the at least one first intermediate core; and
a second core die stack, 20a in Figure 7B, stacked on the first core die stack, the second core die stack including at least one second intermediate core 2b and a second gap filling portion 7b covering an outer surface of the at least one second intermediate core,
wherein the first gap filling portion and the second gap filling portion are directly bonded to each other, at 12, paragraph 44.
In reference to claim 2, Haba discloses each of the at least one first intermediate core and the at least one second intermediate core includes: a substrate 2 in Figure 1; a front insulating layer 5 provided on a front surface of the substrate and having a first bonding pad 6, paragraph 30; and a backside insulating layer, 18 in Figure 5C, provided on a backside surface of the substrate and having a second bonding pad (exposed ends of vias 13) paragraph 41.
In reference to claim 3, Haba discloses the backside insulating layer of the at least one first intermediate core is directly bonded to the front insulating layer of the at least one second intermediate core that is stacked on the at least one first intermediate core, and wherein the second bonding pad of the at least one first intermediate core is directly bonded to the first bonding pad of the at least one second intermediate core that is stacked on the at least one first intermediate core, Figure 9B and paragraph 48.
In reference to claim 4, Haba discloses the front insulating layer 5 and the backside insulating layer 18 include at least one of silicon oxide, silicon nitride, or silicon carbonitride, paragraph 30 and 41.
In reference to claim 5, Haba discloses each of the at least one first intermediate core and the at least one second intermediate core further includes a through electrode 13 that penetrates the substrate and is electrically connected to the first and second bonding pads, paragraph 36.
In reference to claim 6, Haba discloses the first gap filling portion and the second gap filling portion include at least one of an inorganic dielectric or an organic dielectric, paragraph 33.
In reference to claim 7, Haba discloses the first gap filling portion 7b and the second gap filling portion 7a are directly bonded to each other and form a bonding interface layer, Figure 9B and paragraph 48.
In reference to claim 9, Haba discloses a top core die stack on the second core die stack, the top core die stack including a top core and a third gap filling portion covering an outer surface of the top core, paragraph 45.
In reference to claim 10, Haba discloses wherein the third gap filling portion and the second gap filling portion are directly bonded to each other, paragraph 45.
In reference to claim 11, Haba discloses a semiconductor package, comprising:
a buffer die 3, paragraph 29;
a first core die stack, 20b in Figure 7A, stacked on the buffer die, the first core die stack including at least one first intermediate core 2b and a first gap filling portion 7b covering an outer surface of the at least one first intermediate core;
a second core die stack, 20a in Figure 7B, stacked on the first core die stack, the second core die stack including at least one second intermediate core 2a and a second gap filling portion 7a covering an outer surface of the at least one second intermediate core, paragraph 44; and
a top core die stack on the second core die stack, the top core die stack including a top core and a third gap filling portion covering an outer surface of the top core, paragraph 45,
wherein each of the at least one first intermediate core and the at least one second intermediate core includes:
a substrate 2, in Figure 1;
a front insulating layer 5 provided on a front surface of the substrate and having a first bonding pad 6, paragraph 30; and
a backside insulating layer 18 in Figure 5C, provided on a backside surface of the substrate and having a second bonding pad, (exposed ends of vias 13) paragraph 41, and
wherein the first gap filling portion and the second gap filling portion are directly bonded to each other, paragraph 44.
In reference to claim 12, Haba discloses the backside surface of the substrate of the at least one first intermediate core faces the front surface of the substrate of the at least one second intermediate core that is stacked on the at least one intermediate core, Figure 9B and paragraph 48.
In reference to claim 13, Haba discloses wherein the backside insulating layer of the at least one first intermediate core is directly bonded to the front insulating layer of the at least one second intermediate core that is stacked on the at least one first intermediate core, and wherein the second bonding pad of the at least one first intermediate core is directly bonded to the first bonding pad of the at least one second intermediate core that is stacked on the at least one first intermediate core, paragraphs 44 and 48.
In reference to claim 14, Haba discloses the front insulating layer 5 and the backside insulating layer 18 include at least one of silicon oxide, silicon nitride, or silicon carbonitride, paragraph 30 and 41.
In reference to claim 16, Haba discloses each of the at least one first intermediate core and the at least one second intermediate core further includes a through electrode 13 that penetrates the substrate and is electrically connected to the first and second bonding pads, paragraph 36.
In reference to claim 17, Haba discloses the first gap filling portion and the second gap filling portion include at least one of an inorganic dielectric or an organic dielectric, paragraph 33.
In reference to claim 18, Haba discloses the first gap filling portion 7b and the second gap filling portion 7a are directly bonded to each other and form a bonding interface layer, Figure 9B and paragraph 48.
In reference to claim 20, Haba discloses wherein the third gap filling portion and the second gap filling portion are directly bonded to each other, paragraph 45.
In reference to claim 21, Haba discloses a semiconductor package, comprising:
a buffer die 3, paragraph 29;
a plurality of core die stacks sequentially stacked on the buffer die; and
a top core die stack stacked on an uppermost core die stack of the plurality of core die stacks, Figure 8 and paragraphs 44 and 45,
wherein each of the plurality of core die stacks includes at least one intermediate core 2 and a gap filling portion 7 covering an outer surface of the at least one intermediate core, and
wherein the at least one intermediate core includes:
a substrate 2 in Figure 1;
a front insulating layer 5 provided on a front surface of the substrate and having a first bonding pad 6, paragraph 30; and
a backside insulating layer, 18 in Figure 5C, provided on a backside surface of the substrate and having a second bonding pad (exposed ends of vias 13) paragraph 41.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Haba (US 2021/0407941) in view of Yu et al. (US 2022/0344301).
In reference to claims 8 and 19, Haba does not disclose the bonding interface layer has a thickness in a range of 2 Å to 500 Å.
Yu et al. (US 2022/0344301) discloses an analogous semiconductor device including teaching a bonding interface layer having a thickness in a range of 2 Å to 500 Å, paragraph 47. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the bonding interface layer to have a thickness in a range of 2 Å to 500 Å. One would have been motivated to do so in order to provide a bonding interface that can achieve high bonding strength, proper engaging time interval, and low annealing temperature, paragraph 46.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sabatini et al. (US 2010/0244226), Kim et al. (US 2024/0014166), Sasaki et al. (US 7,557,439), Lo (US 2023/0061189) and Zeng et al. (US 2024/0332152), Tsai et al. (US 2023/0386908), and Koyanagi et al. (US 2015/0228622) disclose related chip stack packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
Prosecution Insights