DETAILED ACTION
This Office Action is in response to Application filed April 5, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants' election with traverse of Species I directed to the embodiment shown in Fig. 3 of current application, claims 1, 2, 4, 7-14, 16, 19, 20 and 24-27, in the reply filed on August 19, 2026 is acknowledged. The traversal is on the ground that “Applicant hereby traverses the restriction requirement, at least on the grounds that examination of all of the identified inventions and all of the pending claims would not result in a serious search and/or examination burden.” This is not found persuasive because (a) Applicants did not provide any substantiating evidence that “examination of all of the identified inventions and all of the pending claims would not result in a serious search and/or examination burden”, and (b) on the other hand, Applicants did not provide any evidence that all the species listed in the Restriction Requirement mailed June 22, 2026 are obvious variants from each other as stated in the Restriction Requirement. The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7-14, 16, 19, 20 and 24-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yorikado et al. (WO 2017/094362 assigned to Sony Corporation, not Sony Semiconductor Solutions Corporation of current application; Yorikado et al. (US 2018/0211990) is used as a translation in current Office Action.)
Regarding claims 1, 2, 4 and 7-11, Yorikado et al. disclose a light detecting device (Figs. 1 and 3), comprising: a semiconductor layer (all of semiconductor regions in p-type substrate 109), including: a first pixel (left pixel) ([0046]), the first pixel including a first semiconductor region (107 on left side of middle 201) and a second semiconductor region (105 on left side); and a second pixel (right pixel), the second pixel including a third semiconductor region (107 on right side of middle 201) and a fourth semiconductor region (105 on right side); and a first wiring layer (wiring structure above top surface level of p-type substrate 109), because Applicants’ first wiring layer is not a continuous and contiguous layer, including: a first wiring (middle 201) ([0040]); a first via (104 on left side of middle 201) ([0048]) coupled to the first wiring and the first semiconductor region; a second via (104 on right side of middle 201) coupled to the first wiring (middle 201) and the third semiconductor region; a second wiring (top horizontal portion of 301 on left side) ([0040]), because (a) the limitation “wiring” is directed to a product by process limitation, (b) the second wiring and the third via connected to the second wiring can be formed in a single step, and (c) Applicants do not specifically claim that the second wiring and the third via connected to the second wiring are formed of materials having different material compositions; a third via (vertical portion of 301 on left side) coupled to the second wiring, because the limitation “via” is directed to a product by process limitation as discussed above, and the second semiconductor region; a third wiring (top horizontal portion of 301 on right side), because the limitation “wiring” is directed to a product by process limitation as discussed above; and a fourth via (vertical portion of 301 on right side) coupled to the third wiring, because the limitation “via” is directed to a product by process limitation as discussed above, and the fourth semiconductor region, wherein, in a plan view, the first via (104 on left side of middle 201) is disposed between the third via (vertical portion of 301 on left side) and the fourth via (vertical portion of 301 on right side), and wherein, in the plan view, the second via (104 on right side of middle 201) is disposed between the third via and the fourth via (claim 1), further comprising: a third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3), the third pixel including a fifth semiconductor region (one of p- or n-type semiconductor regions in Fig. 1 identical to or similar to one of first to fourth semiconductor regions in Fig. 3) and a sixth semiconductor region (another of p- or n-type semiconductor regions in Fig. 1 identical to or similar to one of first to fourth semiconductor regions in Fig. 3) (claim 2), further comprising: a fourth wiring (one of wirings in Fig. 1 identical to or similar to one of first to third wirings in Fig. 3); and a sixth via (one of vias in Fig. 1 identical to or similar to one of first to fourth vias in Fig. 3) coupled to the fourth wiring and the sixth semiconductor region, see also the truncation lines on the left and right side of Fig. 3 and the power supply lines 201 on the left and right side of Fig. 3, which signify a repeatedly formed or periodic pixels (claim 4), in the plan view, the first wiring (middle 201) is disposed between the second wiring (top horizontal portion of 301 on left side) and the third wiring (top horizontal portion of 301 on right side) (claims 7 and 8), the first pixel (left pixel in Fig. 3) and the third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3) are disposed in a first direction, see Fig. 1 (claim 9), wherein the first pixel (left pixel in Fig. 3) and the second pixel (right pixel in Fig. 3) are disposed in a second direction perpendicular to the first direction, see the array of pixels in Fig. 1 (claim 10), wherein the second pixel (right pixel in Fig. 3) and the third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3) are disposed in a third direction different than the first direction and the second direction, see the array of pixels in Fig. 1 (claim 11).
Please refer to the explanations of the corresponding limitations above.
Regarding clams 12-14, 16, 19, 20 and 24-27, Yorikado et al. disclose a light detecting device (Figs. 1 and 3), comprising: a semiconductor layer (all of semiconductor regions in p-type semiconductor substrate 109), including: a first pixel (left pixel in Fig. 3), the first pixel including a first semiconductor region (107 on left side of middle 201) and a second semiconductor region (105 on left side); and a second pixel (right pixel in Fig. 3), the second pixel including a third semiconductor region (107 on right side of middle 201) and a fourth semiconductor region (105 on right side); and a first wiring layer (wiring structure above top surface level of p-type substrate 109), including: a first wiring (middle 201); a first via (104 on left side of middle 201) coupled to the first wiring and the first semiconductor region; a second via (104 on right side of middle 201) coupled to the first wiring and the third semiconductor region; a second wiring (top horizontal portion of 301 on left side); a third via (vertical portion of 301 on left side) coupled to the second wiring and the second semiconductor region; a third wiring (top horizontal portion of 301 on right side); and a fourth via (vertical portion of 301 on right side) coupled to the third wiring and the fourth semiconductor region, wherein, in a plan view, at least a portion of the first wiring is disposed between the second wiring and the third wiring (claim 12), further comprising: a third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3), the third pixel including a fifth semiconductor region (one of p- or n-type semiconductor regions in Fig. 1 identical to or similar to first to fourth semiconductor regions) and a sixth semiconductor region (another of p- or n-type semiconductor regions in Fig. 1 identical to or similar to first to fourth semiconductor regions) (claim 13), further comprising: a fourth pixel (yet another pixel in Fig. 1 identical to or similar to Fig. 3), the fourth pixel including a seventh semiconductor region (yet another of p- or n-type semiconductor regions in Fig. 1 identical to or similar to first to fourth semiconductor regions) and an eighth semiconductor region (still yet another of p- or n-type semiconductor regions in Fig. 1 identical to or similar to first to fourth semiconductor regions) (claim 14), further comprising: a fourth wiring (one of wirings in Fig. 1 identical to or similar to one of first to third wirings); and a sixth via (one of vias identical to or similar to one of first to fourth vias) coupled to the fourth wiring and the sixth semiconductor region, see the truncation lines on the left and right side of Fig. 3 and the power supply lines 201 on the left and right side of Fig. 3, which signify a repeatedly formed or periodic pixels (claim 16), wherein in the plan view, at least a portion of the first wiring (middle 201) is disposed between the third wiring and the fourth wiring, see Fig. 1 (claim 19), and in the plan view, at least a portion of the first wiring (middle 201) is disposed between the second wiring (top horizontal portion of 301 on left side) and the fourth wiring, see Fig. 1 (claim 20), the first pixel (left pixel in Fig. 3) and the third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3) are disposed in a first direction, see Fig. 1 (claim 24), wherein the first pixel (left pixel in Fig. 3) and the second pixel (right pixel in Fig. 3) are disposed in a second direction perpendicular to the first direction, see the array of pixels in Fig. 1 (claim 25), wherein the second pixel (right pixel in Fig. 3) and the third pixel (another pixel in Fig. 1 identical to or similar to Fig. 3) are disposed in a third direction different than the first direction and the second direction, see the array of pixels in Fig. 1 (claim 26), wherein the first pixel and the fourth pixel are disposed in a fourth direction different than the first direction, the second direction, and the third direction, see the array of pixels in Fig. 1 (claim 27).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oh et al. (US 10,748,955)
Inoue et al. (US 7,851,879)
Choi et al. (US 10,199,421)
Fan (US 2014/0211056)
Hynecek et al. (US 9,991,306)
Johnson et al. (US 2013/0181309)
Endo et al. (US 9,570,506)
Zhang et al. (US 2014/0291481)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 September 2, 2026
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