DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-14 of U.S. Patent No. 11,955,067. Although the claims at issue are not identical, they are not patentably distinct from each other because the information to be determined is an obvious variation. While patented claim 8 recites symbols (for example bc, p, bt etc.) to represent values that can change or vary, it have been known to use words to describe variables.
8. A display device comprising:
11,955,067 claim 8. A display device, comprising:
a buffer configured to store compressed stress data;
a buffer configured to store compressed stress data;
a decoding circuit configured to receive the compressed stress data for a slice of a display, and to decompress the compressed stress data to obtain reconstructed stress data for the slice:
a decoding circuit configured to receive the compressed stress data for a slice of a display, and to decompress the compressed stress data to obtain reconstructed stress data for the slice of the display;
an adding circuit configured to add additional stress data to the reconstructed stress data to obtain updated stress data for the slice;
an adding circuit configured to add additional stress data to the reconstructed stress data to obtain updated stress data for the slice;
an encoding circuit configured to encode the updated stress data at a first precision level to generate first updated compressed stress data for the slice; and
an encoding circuit configured to encode the updated stress data at a first precision level (pc) to generate first updated compressed stress data for the slice of the display; and
a processor configured to determine a size of the first updated compressed stress data exceeds a size of the buffer, and in response to the size of the first updated compressed stress data exceeding the size of the buffer, to determine a second precision level based on the first precision level and a minimum between a level of precision at which the additional stress data increases a size of the updated stress data and a level of precision at which the buffer increases the size of the first updated compressed stress data,
a processor configured to, in response to a size (bc) of the first updated compressed stress data for the slice of the display exceeding a size (bt) of the buffer, determine a second precision level (p) by performing a calculation using the first precision level (pc), a third precision level (ps) of the additional stress data, and a fourth precision level (pb) of the buffer,
wherein the encoding circuit is further configured to encode the updated stress data at the second precision level to generate second updated compressed stress data that is different than the first updated compressed stress data.
wherein the encoding circuit is further configured to encode the updated stress data at the second precision level (p) to generate second updated compressed stress data that is different than the first updated compressed stress data, wherein the third precision level (ps) of the additional stress data corresponds to a level of precision at which the additional stress data increases a size of the updated stress data, and wherein the fourth precision level (pb) of the buffer corresponds to a level of precision at which the buffer increases a size of the first updated compressed stress data.
9. The display device of claim 8, wherein the processor is further configured to determine the second precision level by setting the second precision level to a sum of the minimum between the level of precision at which the additional stress data increases the size of the updated stress data or the level of precision at which the buffer increases the size of the first updated compressed stress data added to a product of a ratio of the size of the buffer to the size of the first updated compressed stress data multiplied by a difference between the first precision level and the minimum.
11,955,067 claim 9. The display device of claim 8, wherein the processor is further configured to determine the second precision level (p) by setting the second precision level (p) to be equal to [(pc−pm)bt/bc]+pm, wherein pm is a minimum of the third precision level (ps) and the fourth precision level (pb).
10. The display device of claim 9, wherein the processor is further configured to:
11,955,067 claim 10. The display device of claim 9, wherein the processor is further configured to:
determine the level of precision at which the additional stress data increases the size of the updated stress data based on a most significant bit of the additional stress data; and
determine the third precision level (ps) of the additional stress data based on a most significant bit of the additional stress data; and
determine the level of precision at which the buffer increases the size of the first updated compressed stress data based on a most significant bit of data in the buffer.
determine the fourth precision level (pb) of the buffer based on a most significant bit of data in the buffer.
11. The display device of claim 8, wherein the processor is further configured to set the second precision level to a product of the first precision level multiplied by a ratio of the size of the buffer to the size of the first updated compressed stress data.
11,955,067 claim 11. The display device of claim 8, wherein the processor is further configured to determine the second precision level (p) by setting the second precision level (p) to be equal to pc bt/bc.
12. The display device of claim 8, wherein the encoding circuit is further configured to use the first precision level to generate the compressed stress data stored in the buffer.
11,955,067 claim 12. The display device of claim 8, wherein the first precision level (pc) is a precision level used to generate the compressed stress data stored in the buffer.
13. The display device of claim 8, further comprising a dithering circuit configured to add dither to the reconstructed stress data to obtain the updated stress data.
11,955,067 claim 13. The display device of claim 8, further comprising a dithering circuit configured to add dither, in addition to the additional stress data, to the reconstructed stress data to obtain the updated stress data for the slice.
14. The display device of claim 8, further comprising a memory controller configured to store the second updated compressed stress data in the buffer.
11,955,067 claim 14. The display device of claim 8, further comprising a memory controller configured to store the second updated compressed stress data in the buffer.
Claims 1-7 are method claims drawn to the device of claims 8-14 respectively with corresponding substantive claim limitations, and are therefore interpreted and rejected based on similar reasoning.
Claims 15-20 are non-transitory computer readable medium claims drawn to the device of claims 8-11, 13 and 14 respectively with corresponding substantive claim limitations, and are thereof interpreted and rejected based on similar reasoning.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 7, 8, 11, 12, 14, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mobasher et al. (US PGPub 2019/0295510) in view of Croxford et al (US PGPub 2013/0314429).
Regarding claim 8, Mobasher discloses a display device ([0040] and fig. 1, display including display panel 110, processing circuit 115 and memory 120) comprising:
a buffer configured to store compressed stress data (fig. 3 and [0046], “a compressed representation of the stress table is stored in the memory 205”);
a decoding circuit configured to receive the compressed stress data for a slice of a display, and to decompress the compressed stress data to obtain reconstructed stress data for the slice (fig. 3 and [0046], “The compressed stress data are decompressed by a second decoder 310 before being sent to the adding circuit 220”…” the second decoder 310 performs an operation that inverts, or approximately inverts, the operation performed by the encoder 315, i.e., each of the first decoder 305 and the second decoder 310 decompresses data that it receive”):
an adding circuit configured to add additional stress data to the reconstructed stress data to obtain updated stress data for the slice ([0042] and fig. 3, “The adjusted drive current values (which represent the current rate of accumulation of stress of the sub-pixels being displayed) are read by a sub-pixel stress sampling circuit 215 (“Stress Capture” block) and each previously stored stress value is increased (or “augmented”), in an adding circuit 220, by the current rate of accumulation of stress (i.e., by a number proportional to the adjusted drive current value), and saved back to the memory 205”);
an encoding circuit configured to encode the updated stress data at a first precision level to generate first updated compressed stress data for the slice (fig. 3 and [0046], “The encoder 315 encodes data that it receives in a manner that compresses it”); and
a processor ([0041], “The calculations of the predicted loss of optical efficiency, and of the accordingly adjusted drive current, may be performed by the processing circuit”).
While Mobasher discloses various approaches may also be used to reduce the memory size required for storing sub-pixel stress in the stress table ([0046]), it has been known to manage the memory size for a table based on updating the level of encoding if the accumulated amount is too large to store in the memory. In a similar field of endeavor of encoding devices, Croxford discloses wherein the processor is configured to determine a size of the first updated compressed data exceeds a size of the buffer, and in response to the size of the first updated compressed data exceeding the size of the buffer to determine a second precision level based on the first precision level and a minimum between a level of precision at which the additional data increases a size of the updated data and a level of precision at which the buffer increases the size of the first updated compressed data ([0078], “FIG. 5 is a flow diagram schematically illustrating frame-buffer image data formation. This flow diagram assumes that the blocks of data which will be used to form the frame-buffer image data have already been generated and have been marked as static or not static by the processing of FIG. 4. At step 38, the processing waits until a time is reached at which the frame buffer 20 is to be refreshed, e.g. the GPU has been provided with new data by a driver/application and so generates a new frame. At step 40, the blocks of image data generated and marked in the processing of FIG. 4 are searched to identify static portions or portions, i.e. contiguous areas of blocks which are marked as static. Step 42 then determines whether or not the static portion or portions identified in step 40 are greater than a threshold size. If the static portions are too small, or there are no static portions, then it is not worthwhile to adopt large block compression and processing proceeds to step 44 where the whole frame is compressed using small block compression. Conversely, if one or more portions of the image to be compressed are identified as static portions with greater than a threshold size (e.g. multiple neighbouring unchanging regions (blocks) that can be combined together to form large blocks), then the use of large block compression for those portions is justified. Step 46 serves to compress the static portions identified at step 42 with large block compression and step 48 serves to compress the remaining blocks (non-static blocks) with small block compression. A header for the frame-buffer image data stored within the frame memory 20 is written to include data specifying which portions of the frame-buffer image data formed are compressed using large blocks, which are compressed using small blocks and the memory address locations for those different data”),
wherein the encoding circuit is further configured to encode the updated data at the second precision level to generate second updated compressed data that is different than the first updated compressed data ([0078], “Step 46 serves to compress the static portions identified at step 42 with large block compression and step 48 serves to compress the remaining blocks (non-static blocks) with small block compression”).
In view of the teachings of Mobasher and Croxford, it would have been obvious to one of ordinary skill in the art to solve the known problem that when the size of the data exceeds the available memory or storage, decisions could be made on how to handle the overflow by selecting a different level of encoding if there is an overflow as taught by Croxford.
Regarding claim 11, the combination of Mobasher and Croxford further discloses wherein the processor is further configured to set the second precision level to a product of the first precision level multiplied by a ratio of the size of the buffer to the size of the first updated compressed stress data (Mobasher: [0048], “The size of the region of memory allocated to storing the compressed representation of each slice may be fixed or variable based on the compression algorithm used. In one embodiment it can be fixed and selected based on an estimated compression ratio for the coding method used. The compression ratio achieved in operation may vary, however, depending on, for example, the extent to which symbols are repeated in the uncompressed data. When the compression ratio achieved in operation is not sufficiently high to allow the compressed slice to fit within the region of memory allocated to storing the compressed representation of the slice, the raw data may be truncated (i.e., one or more of the least-significant bits of each data word may be removed) before compression is performed, to reduce the size, in memory, of the compressed representation of the slice, so that it will fit within the region of memory allocated to storing the compressed representation of the slice. In another embodiment, the required memory length can be calculated to cover the worst case scenario. In another embodiment, the length of compressed representation can be variable and it is stored in a Table or it is appended to the compressed data”).
Regarding claim 12, the combination of Mobasher and Croxford further discloses wherein the encoding circuit is further configured to use the first precision level to generate the compressed stress data stored in the buffer (Mobasher: [0046] and fig. 3, “the augmented stress values are encoded, or compressed, by an encoder 315, before being stored in the memory 205. The encoder 315 encodes data that it receives in a manner that compresses it, and each of the first decoder 305 and the second decoder 310 performs an operation that inverts, or approximately inverts, the operation performed by the encoder 315, i.e., each of the first decoder 305 and the second decoder 310 decompresses data that it receives. Accordingly, “coding” and “compressing” (and related words, such as “encoding” and “encoded”, and “compressed”, respectively) are used interchangeably herein, as are “decoding” and “decompressing” (and related words, such as “decoded” and “unencoded”, and “decompressed” and “uncompressed”, respectively). Various methods of compression may be employed, including entropy coding, such as Huffman coding or arithmetic coding”).
Regarding claim 14, the combination of Mobasher and Croxford further discloses further comprising a memory controller configured to store the second updated compressed stress data in the buffer (Mobasher: [0042] and figs. 2 and 3, “A memory controller 225 controls read and write operations in the memory, feeds the stress values from the memory to the drive current adjustment circuit 210 and to the adding circuit 220 as needed, and stores the augmented stress values (having been augmented by the addition of the current rate of accumulation of stress) back into memory”).
Claims 1, 4, 5 and 7 are method claims drawn to the device of claims 8, 11, 12 and 14 respectively and are therefore interpreted and rejected based on similar reasoning.
Claims 15, 18 and 20 are non-transitory computer readable medium claims drawn to the device of claims 8, 11 and 14 respectively and are thereof reinterpreted and rejected based on similar reasoning.
Claims 6, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Mobasher and Croxford in view of Lu (US PGPub 2015/0062202).
Regarding claim 13, the combination of Mobasher and Croxford discloses encoding data, however it has been known to use dithering for data compression. In a similar field of endeavor of display devices, Lu further discloses further comprising a dithering circuit configured to add dither to the reconstructed stress data to obtain the updated stress data (Lu: [0009], “Embodiments of the present invention provide for an innovative temporal dithering technique for collecting accumulative data and storing that data in compressed memory. Further embodiments of the present invention provide for a display device, system, and method of accumulating and storing organic light emitting diode (OLED) display color stress data on a pixel-by-pixel basis. Further embodiments are directed to accumulating usage data of a device and its components. Still further embodiments are directed to accumulating statistical data over time in limited storage for later retrieval and use”).
In view of the teachings of Mobasher, Croxford, and Lu, it would have been obvious to one of ordinary skill in the art to include the dithering circuit of Lu within the system of Mobasher and Croxford for the purpose of using dithering to achieve better accuracy of space-constrained accumulations.
Claim 6 is a method claim drawn to the device of claim 13 and is therefore interpreted and rejected based on similar reasoning.
Claim 19 is a computer readable medium claim drawn to the device of claim 13 and is therefore interpreted and rejected based on similar reasoning.
Allowable Subject Matter
Besides the double patenting rejection, claims 2-3, 9-10 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 contains allowable subject matter primarily because the prior art of record does not sufficiently teach or suggest the claimed invention as a whole with regard to the specific calculation used to determine the second precision level. In the exemplary closest prior art, Mobasher discloses a system for stress compensation with compression (fig. 3). It is deemed not obvious to further modify the technique of Mobasher to achieve the differentiating features.
Claim 3 contains allowable subject matter because it depends on claim 2.
Claims 9 and 16 contain allowable subject matter similar to claim 2.
Claims 10 and 17 contain allowable subject matter because they depend on claims 9 and 16 respectively.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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