DETAILED ACTION
Claims 1-20 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 is objected to because of the following informalities:
In the 9th to last line, insert a comma after “storage circuit”.
Claim 10 is objected to because of the following informalities:
In line 2, please delete an “a” from “a a”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 15, “computing system to generate a computer simulation model” and to process “instructions of a hardware description programming language”. From paragraphs 158-160 and 163, the computing system is only described in a generic sense and illustrated as a black box (FIG.21, 2140). Thus, there is insufficient structural disclosure to allow for appropriate 112(f) interpretation. As such, broadest reasonable interpretation (BRI) is taken and 112(a)/(b) rejections appear below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 15, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the computing system to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed functions because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claims 16-20 are rejected due to their dependence on a claim lacking adequate written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 11, “the number of input vectors”. Is this the number of the multiple input vectors, and/or the first and second input vectors of claim 8? The examiner recommends rewording to --a number of input vectors--.
Regarding claim 15, the computing system + function limitation(s) invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, e.g. applicant could claim a circuit instead of a generic system (“circuit” does not invoke 112(f) per MPEP 2181(I)(A), 3rd paragraph);
(b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 16-20 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
Regarding step 1 of the subject matter eligibility test (see flowchart in MPEP 2106(III)), all claims are directed to a statutory category of invention.
Regarding step 2A (prong 1) of the test (see flowchart in MPEP 2106.04(II)(A), claim 1 recites:
write multiple input vectors such that elements of a given input vector are split among multiple columns of the plurality of columns, and a given row of the plurality of rows has interleaved elements of the multiple input vectors, forming interleaved rows for the plurality of rows, wherein writ[ing] the multiple input vectors includes writ[ing], during a first time period, all elements of a first input vector of the multiple input vectors to a first subset of the plurality of columns; and writ[ing], during a second time period subsequent to the first time period, all elements of a second input vector of the multiple input vectors to a second subset of the plurality of columns, wherein the second subset is disjoint from the first subset.
These steps corresponds to the abstract idea grouping of mental processes that can be performed in the human mind using pen and paper (MPEP 2106.04(a)(2)). This mental process includes evaluating or judging how to rearrange/organize data so that it is interleaved. FIGs.12A-E are an example of how the mental process could be carried out using pen and paper, where a human, given a group of input vectors 1202A, can judge which elements of input vectors need to be placed where in an array as shown in FIGs.12B-E. By writing them down as shown, a human performs the process of interleaving vector data. The first time period referenced above would correspond to the human creating FIG.12B on paper. The second time period referenced above would correspond to the human adding two more columns of elements to FIG.12B to arrive at FIG.12C.
Regarding step 2A (prong 2) of the test, claim 1 recites additional elements of:
an execution circuit within an execution pipeline of a processor, the execution circuit comprising:
a first array storage circuit configured to store elements of a first array having a plurality of rows and a plurality of columns;
a first input write port; and
a first output write port; and
a control circuit configured to:
receive multiple input vectors;
using the first input write port, perform the writing;
using the first output write port, output data corresponding to the interleaved rows to form one or more result values;
write, during a first clock cycle, to the first subset; and
write, during a second clock cycle, to the second subset.
All components (execution circuit, pipeline, processor, first array storage circuit, write ports, control circuit) are recited with a high-level of generality so as to amount to a generic computer being used as a tool to implement the abstract idea. Using a generic computer as a tool has been determined by the courts to not integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I), 6th bullet).
The steps to store elements of a first array having rows/columns, receive the multiple input vectors, write the multiple input vectors to the storage circuit, and output the data to form results, all performed by a generic circuit in a number of clock cycles, are deemed insignificant extra-solution activity that are incidental to the mental process itself and only a nominal or tangential addition to the claim. The courts have similarly determined such activity to not integrate the abstract idea into a practical application (see MPEP 2106.04(d)(I), 7th bullet).
Finally, the examiner notes that writing multiple columns in a single cycle constitutes generically linking the use of the mental process to a parallel processing environment (meaning multiple tings/writes can occur at once), which again does not integrate into a practical application (MPEP 2106.04(d)(I), 8th bullet).
Thus, the additional elements, alone or in combination, do not integrate the claimed mental process into a practical application.
Regarding step 2B of the test, as it pertains to claim 1:
As stated above, the generic components amount to a generic computer used as a tool to perform the mental process. The courts have determined that such does not amount to significantly more (see MPEP 2106.05(I)(A), second item (i)).
Additionally, the receiving, writing/storing to memory over a period of time, and outputting are, per the courts, all highly-generic, well-understood, routine, and conventional functions that do not amount to significantly more (see MPEP 2106.05(d)(I) and (II), first items (i) and (iv)).
Finally, the generic linking to a parallel environment does not amount to significantly more, per the courts (see MPEP 2106.05(I)(A), second item (iv)).
Thus, the additional elements, alone or in combination do not amount to significantly more, and claim 1 is patent-ineligible under 35 U.S.C. 101.
Claims 2-3 encompass the mental process shown in FIGs.13A-E and similar additional elements as claim 1. Thus, for similar reasoning, the additional elements do not integrate the mental processes into a practical application, nor do they amount to significantly more. Claims 2-3 are therefore patent-ineligible under 35 U.S.C. 101.
Claims 4-5 encompass more details of the mental process shown in FIGs.12A-E and similar additional elements as claim 1. Thus, for similar reasoning, the additional elements do not integrate the mental process into a practical application, nor do they amount to significantly more. Claims 4-5 are therefore patent-ineligible under 35 U.S.C. 101.
Claim 6 sets forth a buffer to buffer the data emptied from the storage circuit. This buffer, as claimed, is a generic computer component that does not integrate the abstract idea into a practical application nor does it amount to significantly more. Buffering is also deemed insignificant post-solution activity that is a mere nominal addition to the claim. Thus, it does not integrate the abstract idea into a practical application. Note, from MPEP 2106.05(a), last paragraph (item vii), that the courts have identified buffering content as well-known, routine, and conventional. As such, this activity does not amount to significantly more.
Claim 7 sets forth an additional element of a second storage circuit to store more input vectors while the outputting from the first array storage circuit occurs. Again, this amounts to high-level recitation of generic computer components to perform multiple tasks in parallel. That is, parallel machines that do two or more things simultaneously are generic. Thus, claim 7 is not patent-eligible because it does not integrate the mental process into an abstract idea, nor does it amount to significantly more.
Claims 8-9 are not patent-eligible for similar reasoning as claim 1.
Claims 10-11 merely expand on the mental process and thus are not patent-eligible.
Claims 12-14 are not patent eligible for similar reasoning as claims 2 and 6-7, respectively.
Claim 15 is mostly not patent eligible for similar reasoning as claim 1. Claim 15 additionally recites the element of the “medium having instructions of a hardware description programming language…to generate a model…”. However, this simply amounts to a generic computer component to implement the abstract idea on a generic computer, which again does not integrate the abstract idea into a practical application, nor does it amount to significantly more.
Claims 16-17 merely set forth more generic elements that do not integrate and do not amount to significantly more.
Claim 18 merely expands on the mental process and thus is not patent eligible.
Claims 19-20 are not patent eligible for similar reasoning as claims 6-7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 8, 11, 13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sade et al. (US 2019/0102196, as cited by applicant), in view of the examiner’s taking of Official Notice.
Referring to claim 1, Sade has taught an apparatus, comprising:
an execution circuit within an execution pipeline (FIG.13 and paragraph 18) of a processor, the execution circuit comprising:
a first array storage circuit configured to store elements of a first array having a plurality of rows and a plurality of columns (FIG.21, 2116, which may be a collection of vector registers (paragraph 167). From paragraphs 113-114, a word includes 16 bits. From paragraph 167, the elements in FIG.21 are 16-bit words. This means that each row in 2116 would be a 256-bit ymm register (FIG.27, 2710) to store sixteen 16-bit words. In other words, in the example in FIG.21, the first array storage circuit 2116 comprises two ymm vector registers to store a plurality of rows/columns);
a first input write port (FIG.21, port receiving data from 2114);
a first output write port (FIG.21, port sending data from 2116 to 2118); and
a control circuit (FIG.21, 2114) configured to:
receive multiple input vectors (FIG.21, vectors (e.g. rows) in 2112);
using the first input write port, write the multiple input vectors to the first array storage circuit such that:
elements of a given input vector are split among multiple columns of the plurality of columns (from FIG.21, a given input vector, e.g. top row in 2112, is written such that its elements are in different columns in 2116); and
a given row of the plurality of rows has interleaved elements of the multiple input vectors, forming interleaved rows for the plurality of rows (from FIG.21, the top row of 2116 has interleaved elements of the top two row vectors of 2112); and
using the first output write port, output data corresponding to the interleaved rows to form one or more result values (the row data in 2116 is outputted to 2118), wherein to write the multiple input vectors to the first array storage circuit the control circuit is configured to:
write all elements of a first input vector of the multiple input vectors to a first subset of the plurality of columns (from FIG.21, all elements of a first input vector (top row in 2112) are written to a subset of columns, i.e., to columns 0, 2, 4, 6, 8, 10, 12, and 14 (with the leftmost column in 2116 being column 0); and
write all elements of a second input vector of the multiple input vectors to a second subset of the plurality of columns, wherein the second subset is disjoint from the first subset (from FIG.21, all elements of a second input vector (bottom row in 2112) are written to a subset of columns, i.e., to columns 1, 3, 5, 7, 9, 11, 13, and 15).
Sade has not taught the timing of the writes, i.e., that writing all elements of the first input vector occurs during a first clock cycle of the processor, and that writing all elements of the second input vector occurs during a second clock cycle subsequent to the first clock cycle. However, Official Notice is taken that a register file (including a vector register file) with a single write port was well-known in the art before applicant’s invention. Fewer write ports equates to less circuitry/wiring (reduced wiring complexity) and a smaller register file footprint. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sade such that the vector register file including the registers making up 2116 only has a single write port, meaning only one vector register may be written per cycle. With such a modification, the data in FIG.21 would be written to two different ymm registers in two different clock cycles (first and second).
Referring to claim 6, Sade, as modified, has taught the apparatus of claim 1, but has not taught a buffer circuit configured to store data output from the first array storage circuit, and wherein the control circuit is further configured to empty the first array storage circuit during a given clock cycle of the processor by sending data corresponding to each of the plurality of rows to either an entry of the buffer circuit or a data port of execution circuit. However, Official Notice is taken that storing data to a store buffer for ultimate writing to main memory was well known in the art before applicant’s invention. This allows data to be moved to storage for later retrieval while freeing up fast registers for processing current data. For example, in FIG.21, destination 2116 may be a “reg” (register) location, from instruction field 2104. As is known, to then store this data to a different memory, a store instruction would be used to move the data to a store buffer, where it will wait until it can be written to memory. A store buffer decouples the storing process from the processor itself. That is, a processor may need to wait to store data while the memory is busy doing something else, if there is no store buffer. This causes a decrease in performance. With a store buffer, the processor can empty the data from the register to the store buffer and proceed with processing while the memory controller finishes the storing when the storing is able to proceed. As a result, in order to store data to memory in an efficient manner, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sade to include a buffer circuit configured to store data output from the first array storage circuit, and wherein the control circuit is further configured to empty the first array storage circuit during a given clock cycle of the processor by sending data corresponding to each of the plurality of rows to either an entry of the buffer circuit or a data port of execution circuit.
Claim 8 is rejected for similar reasoning as claim 1.
Referring to claim 11, Sade, as modified, has taught the method of claim 8, wherein:
the elements of the first input vector (FIG.21, top row in 2112) are split among multiple columns (FIG.21, columns 0, 2, 4, etc.) of the first subset of the plurality of columns; and
the multiple columns of the first subset of the plurality of columns are spaced apart from one another in the first array by a number of columns equal to the number of input vectors (columns 0, 2, 4, 6, etc. are spaces apart by 2 columns, which is the number of input vectors (the top and bottom rows are the input vectors)).
Claim 13 is rejected for similar reasoning as claim 6.
Claim 15 is mostly rejected for similar reasoning as claim 1. Sade has further taught a non-transitory computer readable medium having instructions of a hardware description programming language stored thereon (paragraphs 311-312). Sade has not taught that the instructions, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware execution circuit for a pipeline of a processor. However, Official Notice is taken that executing HDL code to generate a model of an entire processor (or any component within it) for simulation was well-known in the art before applicant’s invention. Such allows for testing/debugging the hardware design in software prior to fabrication, to ensure correct operation. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sade such that the instructions, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware execution circuit for a pipeline of a processor
Referring to claim 16, Sade, as modified, has taught the computer readable medium of claim 15, wherein the computer simulation model further represents the processor (see the rejection of claim 15. Also, from paragraph 311, an “IP core” (processor) may be generated. It is obvious to simulate the entire core/processor).
Referring to claim 17, Sade, as modified, has taught the computer readable medium of claim 16, wherein the processor is a coprocessor configured to perform vector and matrix operations (see paragraph [0272]).
Referring to claim 18, Sade, as modified, has taught the computer readable medium of claim 15, wherein:
the first array has M columns and N rows (from FIG.21, the first array has M=16 columns and N=2 rows); and
M is a multiple of N by a factor P (M=16 is a multiple of N=2 by a factor of P=8).
Claim 19 is rejected for similar reasoning as claim 6.
Claims 2-3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sade in view of the examiner’s taking of Official Notice and Symes et al. (US 2010/0106944, as previously cited).
Referring to claim 2, Sade, as modified, has taught the apparatus of claim 1, but has not taught wherein the control circuit is further configured to: receive multiple interleaved input values; using the first input write port, write the multiple interleaved input values to the first array storage circuit such that: elements of a given interleaved input value are split among multiple columns of a given subset of the plurality of columns; and a given row of the plurality of rows has ordered elements of a vector, forming vector rows for the plurality of rows; and using the first output write port, output data corresponding to the vector rows to form one or more vector result values. In other words, Sade has not taught the reverse (de-interleaving) of FIG.21 (which shows interleaving). However, Symes has taught using the same circuitry to perform both an interleave and de-interleave (see FIGs.68A-69C). Such would allow for increased flexibility in the number/types of operations that can be supported while also efficiently using the same circuitry based on different controls. Going in the reverse of FIG.21 would operate as claimed. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sade such that the control circuit is further configured to: receive multiple interleaved input values; using the first input write port, write the multiple interleaved input values to the first array storage circuit such that: elements of a given interleaved input value are split among multiple columns of a given subset of the plurality of columns; and a given row of the plurality of rows has ordered elements of a vector, forming vector rows for the plurality of rows; and using the first output write port, output data corresponding to the vector rows to form one or more vector result values.
Referring to claim 3, Sade, as modified, has taught the apparatus of claim 2, wherein the multiple columns of the given subset are adjacent to one another in the first array (see FIG.21 and note that going in reverse (from data 2116 to 2112) would put interleaved values (0.0, 0.1, 0.2, etc. into adjacent columns (as shown in 2112)).
Claim 12 is rejected for similar reasoning as claim 2.
Claims 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sade in view of the examiner’s taking of Official Notice and Coffin, III et al. (US 2003/0172326).
Referring to claim 7, Sade, as modified, has taught the apparatus of claim 1, but has not taught a second array storage circuit configured to store elements of a second array, and wherein the control circuit is further configured to write additional input vectors to the second array storage circuit while outputting the data corresponding to the interleaved rows from the first array storage circuit. However, Coffin has taught ping-pong processing where one buffer is receiving input while another buffer is sending output. Then the two buffers swap roles. This would allow Sade to perform more interleaving while the result of the previous interleaving is being outputted to further logic, thereby providing a constant stream of input and output (see paragraph [0038] of Coffin) so as to keep logic busy at all times and improve throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sade to include a second array storage circuit configured to store elements of a second array, and wherein the control circuit is further configured to write additional input vectors to the second array storage circuit while outputting the data corresponding to the interleaved rows from the first array storage circuit.
Claims 14 and 20 are rejected for similar reasoning as claim 7.
Allowable Subject Matter
Claims 4-5 and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Note that any amendments to these claims may affect their allowability.
Response to Arguments/Amendments
In response to the amendments and arguments made by applicant in response to the 112 rejections, the 112 rejections have been withdrawn.
In argument A starting on page 13 of applicant’s response, applicant argues that applicant’s claims are directed to a specialized execution circuit that addresses technological problems by not tying up registers of a pipeline.
This is not persuasive. While applicant sees the claim as setting forth specialized circuitry, it is claimed as generic circuitry comprising nothing but generic components. Further, the first array storage circuit is broad enough to encompass traditional registers. Therefore, the claim is not reflective of the improvement, which is allegedly that registers are not tied up. The claim must reflect the improvement, and the improvement must come from an additional element, not the abstract idea alone.
In argument B starting on page 15 of the response, applicant argues that claims directed to an improvement are patent eligible.
The examiner agrees but the claims do not presently reflect an improvement from the examiner’s perspective, at least in part because applicant’s claims are broad enough to tie up registers when applicant is arguing that the improvement is not tying up registers. The claims are broad enough to encompass a generic computer performing the mental process of interleaving.
In argument C starting on page 16 of the response, applicant argues that the claimed specialized circuitry is separate from typical storage elements such as a register file or data buffer.
The examiner respectfully disagrees. There is nothing in the claims that would preclude the storage circuit from including registers (or some other generic storage).
In argument D1, applicant argues that applicant is not attempting to tie up the alleged judicial exception of interleaving, and that the claims are directed to a clear improvement.
The examiner respectfully disagrees since the claim only recites highly-generic structural elements. In other words, applicant is simply using generic components to perform interleaving. Further, as explained above, the examiner does not believe any improvement is clearly reflected by the claim so as to pass the streamlined analysis.
In argument D2, applicant argues that the examiner has ignored that the claim recites writing input vectors to an array storage circuit, an action that cannot be performed mentally.
The examiner agrees that writing to storage circuitry is not abstract. However, the examiner never stated that it was. Interleaving data is abstract. This can be done by a human with pen and paper. The generic writing to generic storage is an additional element that amounts to insignificant extra solution activity involving a generic computer component (storage). This was addressed as an additional element in the rejection.
In argument D2, applicant also argues that a human mind cannot write data in a clock cycle of a processor.
The examiner also agrees here. However, as explained in the rejection, a human interleaving data by carrying out a mental process on paper as shown in FIGs.12B-E would occur over multiple units of time. During a first unit of time, FIG.12B will be written. Then during a next unit of time, the new data introduced in FIG.12C will be written. A processor operates in units of time called clock cycles. Thus, when the abstract idea is ported from the mind to a generic computer, it will be similarly performed in the processor’s time units, i.e., over multiple clock cycles. Writing two columns at a time can’t be practically performed by a human, but can be by a generic parallel processor. In other words, applicant is merely claiming a way to speed up the interleaving by linking to a parallel environment to perform multiple writes to generic storage at once.
With respect to argument D3, the examiner maintains that the additional elements, as claimed, are merely generic in nature. Applicant appears to be focusing on circuitry that does not include registers (separate from a register file). However, this is not claimed. The examiner also would like to remind applicant of the breadth of negative limitations should applicant choose to amend to make this separation more clear. For instance, saying that the circuitry is separate from a given register file does not mean that the circuitry cannot be another type of register file that is separate from the given register file (as a broad example, if integer registers of a register file could be used to store the interleaved data, but a floating-point register file also exists in the system, then the storage circuit could still be both an integer register file and separate from a register file (floating-point register file)).
With respect to argument D4, the issue is the breadth of claims like claim 6. Claim 6 encompasses a generic store buffer to accept data from registers (as in the case of a normal store instruction storing data from the registers to memory). For claim 7, again, applicant is just linking to a parallel/pipelined environment where multiple tasks can be performed at once.
In argument E, applicant argues that the interleaving cannot be practically performed in the human mind.
The examiner respectfully disagrees. A human, given inputs of FIG.12A and a rule with how to interleave the inputs, can mentally arrive at the final output in FIG.12E using pen and paper. This involves evaluating/judging how to rearrange data according to an algorithm practically performed in the human mind to arrive at a particular result. The examiner believes that this is an entirely different level of practical mental activity that that in SRI Int’l, Inc. v. Cisco Systems, Inc., as cited by applicant.
In argument E, applicant expresses concern that presence of a drawing indicates subject matter ineligibility.
The presence per se is not an indicator. The examiner is merely pointing to FIG.12 as a way a human could use pen and paper to show the interleaving.
On page 22 of the response, applicant argues that the cited references do not teach writing elements from different input vectors during different clock cycles.
The examiner agrees. However, such is deemed obvious as seen in the prior art rejections above.
At the end of page 22, applicant argues that Official Notice with respect to the Ould rejection is improper.
The examiner disagrees but this argument is moot since the examiner has withdrawn the rejection for the time being to focus on the 101 and Sade rejections.
On page 23 of the response, applicant argues that storing data to a store buffer is not capable of instant and unquestionable demonstration of being well-known.
This is not persuasive because it amounts to a mere allegation without a supporting explanation as to why it is not well-known, as required by MPEP 2144.03(C). Thus, a supporting reference is not required at this time.
On page 23 of the response, applicant argues that the Official Notice is improper because it cannot be used as the principal evidence upon which a rejection is based.
The examiner asserts that Official Notice is not the principal evidence. Sade is the principal evidence. Claim 6, due to its breadth, merely sets forth a well-known peripheral issue, which is appropriately addressed with Official Notice.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Van Kampen, US 2013/0091339, has taught receiving input vectors and iteratively interleaving them as shown in FIG.10 and paragraph 93.
Blomgren, US 2002/0198911, has taught rearranging data between vector and matrix form in a SIMD matrix processor.
Bainville, US 2019/0310854, has taught an engine with interleave and deinterleave options.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183