DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-18 in the reply filed on 7/29/26 is acknowledged. The traversal is on the ground(s) that the restriction requirement is respectfully traversed in order to preserve the issue for subsequent petition since examination of the claims of each of the Groups is not believed to create an undue burden on the Office. To be proper, a requirement for restriction must meet two criteria: (A) the inventions must be independent or distinct as claimed; and (B) there would be a serious burden on the examiner if restriction is not required. See MPEP @ 803. This is not found persuasive because the examiner has provided the distinction between the product and process in that the product does not require partially mitigate transfer of chip-package interaction (CPI) stress from the bump to the die. Specifically, the process claim only focuses on the process of making the device, the partial mitigation transfer of the chip-package interaction (CPI) stress is not considered in this process only in the device.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 9/18/24. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US PGPub 2019/0164860, hereinafter referred to as “Lin”).
Lin discloses the semiconductor device as claimed. See figures 1-18 and corresponding text, where Lin teaches, in claim 1, a device comprising: (figures 15-18; [0036-0046])
a die (50) that is at least partially encapsulated (110), the die comprising a conductive pad (126);
a first passivation layer (114) coupled to a first surface of the die (50);
an offset interconnect (132) extending along a surface of the first passivation layer (116) and including a portion that extends through an opening in the first passivation layer (116) to contact the conductive pad (126); and
a bump (136) including a portion that extends through an opening in a second passivation layer (116) to contact the offset interconnect (132), wherein the bump (136) is offset, in a direction along a surface of the second passive layer (116), from the conductive pad (126).
Lin teaches, in claim 2, wherein the offset interconnect is configured to at least partially mitigate transfer of chip-package interaction (CPI) stress from the bump to the die ([0048]).
Lin teaches, in claim 3, further comprising mold contacting one or more sidewalls of the die, at least a portion of the first passivation layer, and at least a portion of the offset interconnect (figures 15-18; [0036-0046]).
Lin teaches, in claim 4, wherein the offset interconnect comprises a portion of a planarized bump (figures 15-18; [0036-0046]).
Lin teaches, in claim 5, wherein the offset interconnect extends away from the conductive pad in a horizontal direction (figures 15-18; [0036-0046]).
Lin teaches, in claim 6, wherein the offset interconnect extends along the horizontal direction such that a footprint of the bump and a footprint of the portion of the offset interconnect that extends through the opening in the first passivation layer do not overlap (figures 15-18; [0036-0046]).
Lin teaches, in claim 7, further comprising: (figures 15-18; [0036-0046])
a substrate; and
one or more additional dies, wherein the die and the one or more additional dies are coupled to the substrate.
Lin teaches, in claim 8, further comprising:
mold coupled to the substrate, to the die, and to the one or more additional dies; and
an offset bump planarized with the mold to form the offset interconnect (figures 15-18; [0036-0046]).
Lin teaches, in claim 9, wherein the conductive pad is disposed on a first side of the die, and further comprising:
a die interconnect layer having a first side;
a second side of the die coupled to the first side of the die interconnect layer; and
a second die coupled to a second side of the die interconnect layer (figures 15-18; [0036-0046]).
Lin teaches, in claim 10, wherein the die at least partially overlaps the second die (figures 15-18; [0036-0046]).
Lin teaches, in claim 11, a device comprising:
a die (50) that is at least partially encapsulated (110), the die comprising a conductive pad (126);
a passivation layer (116) coupled to a surface of the die (50); and
a bump (136) electrically coupled to the conductive pad (126) via an offset interconnect (132) that is configured to transfer forces applied to the bump (136) to the passivation layer (figures 15-18; [0036-0046]).
Lin teaches, in claim 12, wherein the offset interconnect comprises:
a first portion that extends through an opening in the passivation layer to contact the conductive pad; and
a second portion that extends along a surface of the passivation layer to connect to a portion of the bump (figures 15-18; [0036-0046]).
Lin teaches, in claim 13, further comprising a second passivation layer, wherein the bump includes a portion that extends through an opening in the second passivation layer to contact the offset interconnect (figures 15-18; [0036-0046]).
Lin teaches, in claim 14, further comprising mold contacting one or more sidewalls of the die, at least a portion of the passivation layer, and at least a portion of the offset interconnect (figures 15-18; [0036-0046]).
Lin teaches, in claim 15, wherein the offset interconnect extends away from the conductive pad in a horizontal direction such that a footprint of the bump does not overlap a footprint of an interface between the offset interconnect and the conductive pad (figures 15-18; [0036-0046]).
Lin teaches, in claim 16, further comprising:
a substrate; and
one or more additional dies, wherein the die and the one or more additional dies are coupled to the substrate and separated by mold (figures 15-18; [0036-0046]).
Lin teaches, in claim 17, further comprising: a die interconnect layer having a first side;
a second side of the die coupled to the first side of the die interconnect layer; and
a second die coupled to a second side of the die interconnect layer (figures 15-18; [0036-0046]).
Lin teaches, in claim 18, wherein the die at least partially overlaps the second die (figures 15-18; [0036-0046]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 30, 2026
