CTNF 18/628,856 CTNF 84655 DETAILED ACTION Notice of AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. IDS The IDS document(s) filed on April 8, 2024 and July 21, 2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “continuous silicon substrate” of claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Additionally, it is unclear what the unlabeled layer shown below in corresponding FIG. 45 is. PNG media_image1.png 429 534 media_image1.png Greyscale Additionally, the “N2P space” of claims 3, 10, and 16 is not illustrated in corresponding FIG. 44. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections – 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. § 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 Claims 1-7, 10, and 16 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claim 1, it is unclear how “a height of the backside dielectric layer in the logic device region is substantially equal to a height of the continuous silicon substrate in the passive device region” (emphasis added). The continuous silicon substrate is not illustrated or labeled in corresponding FIGS. 42-45. Applicant’s published specification paragraph [0034] also describes base substrate 112, which may comprise silicon, as being sacrificial and not present in the final structure. As to claim 1, it is unclear what is meant by “substantially equal”. The term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. As to claims 3, 10, and 16, there is a lack of antecedent basis for “ the N2P space” (emphasis added). As to claim 16, it is unclear if “a dielectric etch stop layer” refers to a new dielectric etch stop layer or the same layer recited in parent claim 15. Claim Rejections 35 U.S.C. § 102(a)(2) 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1, 2, 15 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Kim et al. (U.S. Patent Publication No. 2024/0332185 A1), hereafter “Kim” . As to claim 1, Kim teaches: A logic device region 101 comprising logic devices having backside contact structures 126+187 embedded in a backside dielectric layer 114 . See Kim, FIG. 12. A passive device region 102 comprising passive devices on a continuous silicon substrate (112 or 118) . Wherein a height of the backside dielectric layer in the logic device region is substantially equal to a height of the continuous silicon substrate in the passive device region. The Examiner notes that claim 1 does not define “a height of the backside dielectric layer”. As such, “a height of the backside dielectric layer” could comprise only a portion of the full height of the backside dielectric layer, wherein the portion is exactly equal to a height of the thinner continuous silicon substrate (112 or 118). Alternatively, a full height of the backside dielectric layer is substantially , i.e. largely but not wholly, equal to a height of the continuous silicon substrate. As to claim 2, Kim teaches a dielectric etch stop layer 116 physically separating the backside dielectric layer 114 from another backside dielectric layer 141. The Examiner notes that “etch stop” is process language that does not structurally limit the claim. As to claim 15, Kim teaches: A logic device region 101 comprising logic devices having backside contact structures 126+187 embedded in a backside dielectric layer 114 . Id. A passive device region 102 comprising passive devices on a continuous silicon substrate (112 or 118) . A dielectric etch stop layer 116 physically separating the first backside dielectric layer from a second backside dielectric layer 141 . The Examiner notes that “etch stop” is process language that does not structurally limit the claim. Claims Allowable If Rewritten in Independent Form 12-151-08 AIA 07-43 12-51-08 Claim s 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claim 17, Kim does not teach backside via structures nor shallow trench isolation regions. As to claim 18, Kim does not teach a further placeholder directly beneath a source drain region because Kim’s placeholder 187 was used to correspond to the previously claimed backside contact structures embedded in a first backside dielectric layer. As to claims 19 and 20, Kim does not teach shallow trench isolation regions. Indication of Allowable Subject Matter 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: claims 8, 9, and 11-14 are indicated as being allowable because Kim teaches a logic device region 101 comprising logic devices having backside contact structures 126+187 embedded in a first backside dielectric layer 114; a passive device region 102 comprising passive devices on a continuous silicon substrate 112 or 118; and a second backside dielectric layer 189 (mask layer, may comprise oxynitride) below the first backside dielectric layer in the logic device region and below the continuous silicon substrate in the passive device region. However, Kim does not teach “wherein a topmost surface of the second backside dielectric layer is above a bottommost surface of the first backside dielectric layer” because the two surfaces touch and are coplanar . No Prior Art Applied The Examiner was unable to find prior art applicable to claims 3-7 as presently written. As to claims 3, 4, 6, and 7, Kim does not teach shallow trench isolations. As to claim 5, Kim does not teach a further placeholder directly beneath a source drain region because Kim’s placeholder 187 was used to correspond to the previously claimed backside contact structures embedded in a first backside dielectric layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893 Application/Control Number: 18/628,856 Page 2 Art Unit: 2893 Application/Control Number: 18/628,856 Page 3 Art Unit: 2893 Application/Control Number: 18/628,856 Page 4 Art Unit: 2893 Application/Control Number: 18/628,856 Page 7 Art Unit: 2893 Application/Control Number: 18/628,856 Page 8 Art Unit: 2893
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