DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/31/2025 have been fully considered but they are not persuasive. Examiner respectfully disagrees with the applicant’s argument that “cited references, even in combination, do not teach or suggest "a sixth transistor connected between the first node and the third node, and including a gate electrode electrically connected to the second scan line, a first electrode directly connected to the first node and a second electrode directly connected to the third node." Applicant asserts that “For example, the alleged sixth transistor T6 in KANG and the alleged sixth transistor M2 in CHUNG do not have a first electrode directly connected to the first node and a second electrode directly connected to the third node”. Examiner respectfully disagrees.
Kang teaches a sixth transistor (T6 in Fig. 2B) connected between the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B) and the third node (N5 in Fig. 2B), and including a gate electrode (gate electrode of transistor T6 in Fig. 2B) electrically connected to the second scan line (SL2i in Fig. 2B;[0076]; note that the claim does not recite a gate electrode “directly” connected to the second scan line. All the elements in Fig. 2B are connected to each other), a first electrode (first electrode of transistor T6 in Fig. 2B) directly connected to the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B) and a second electrode (second electrode of transistor T6 in Fig. 2B) directly connected to the third node (N5 in Fig. 2B), as claimed.
Chung teaches a sixth transistor (M2 in Fig. 5) connected between the first node (N2 in Fig. 5) and the third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and including a gate electrode (gate electrode of transistor M2 in Fig. 5) electrically connected to the second scan line (S1n line in Fig. 5), a first electrode (first electrode of transistor M2 in Fig. 5) directly connected to the first node (N2 in Fig. 5) and a second electrode (second electrode of transistor M2 in Fig. 5) directly connected to the third node (node directly connecting transistor M2 and data line Dm in Fig. 5),
as claimed.
The cited prior art teaches applicant’s claimed invention as noted in the office action below.
Claim Objections
Claim 8 is objected to because of the following informalities:
As to claim 8, the phrase “is directed connected” in line 2 of the claim should be changed to is “directly connected”, in order or to be grammatically correct. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2023/0154403 A1).
As to claim 1, Kang teaches a pixel ([0002]: pixel) comprising: a first transistor (T1 in Fig. 2B) including a gate electrode connected to a first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B; note that the claim does not recite a gate electrode directly connected to a first node; All of the elements in Fig. 2B are connected to each other), a first electrode (first electrode of transistor T1 in Fig. 2B) electrically connected to a first power line configured to supply first driving power (VDD in Fig. 2B;[0068]: first power source VDD;[0112]), and a second electrode (second electrode of transistor T1 in Fig. 2B) connected to a second node (N4 in Fig. 2B);
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a second transistor (T2_2 in Fig. 2B) including a first electrode (first electrode of transistor T2_2 in Fig. 2B) electrically connected to a data line (DLj line in Fig. 2B;[0076]: data line DLj; note that the claim does not recite a first electrode directly connected to a data line. All the elements in Fig. 2B are connected to each other), a second electrode (second electrode of transistor T2_2 in Fig. 2B), and a gate electrode (gate electrode of transistor T2_2 in Fig. 2B) electrically connected to a first scan line (SL1i line in Fig. 2B;[0076]: scan line SL1i); a third transistor (T2_1 in Fig. 2B) connected between the data line (DLj in Fig. 2B;[0076]: data line DLj) and a third node (N5 in Fig. 2B), and including a gate electrode (gate electrode of transistor T2_1 in Fig. 2B) electrically connected to a second scan line (SL2i in Fig. 2B;[0076]; note that the claim does not recite a gate electrode directly connected to a second scan line. All the elements in Fig. 2B are connected to each other) which is different from the first scan line (SL1i line in Fig. 2B;[0076]: scan line SL1i), the third transistor (T2_1 in Fig. 2B) being directly connected to the data line (DLj in Fig. 2B;[0076]: data line DLj); a fourth transistor(T7 in Fig. 2B) connected between the second node (N4 in Fig. 2B) and the third node (N5 in Fig. 2B), and including a gate electrode (gate electrode of transistor T7 in Fig. 2B) electrically connected to an emission control line (EL2i line in Fig. 2B;[0105]);
a sixth transistor (T6 in Fig. 2B) connected between the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B) and the third node (N5 in Fig. 2B), and including a gate electrode (gate electrode of transistor T6 in Fig. 2B) electrically connected to the second scan line (SL2i in Fig. 2B;[0076]; note that the claim does not recite a gate electrode directly connected to the second scan line. All the elements in Fig. 2B are connected to each other), a first electrode (first electrode of transistor T6 in Fig. 2B) directly connected to the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B) and a second electrode (second electrode of transistor T6 in Fig. 2B) directly connected to the third node (N5 in Fig. 2B);
a first capacitor (C2_1 in Fig. 2B) including a first electrode connected to the second electrode of the second transistor (second electrode of transistor T2_2 in Fig. 2B) and a second electrode connected to the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B); a second capacitor (C2 in Fig. 2B) connected between the first power line (VDD in Fig. 2B) and the first node (first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B); and a light emitting element (LD in Fig. 2B) connected between the third node (N5 in Fig. 2B) and a second power line configured to supply second driving power (VSS in Fig. 2B;[0076]).
As to claim 2, Kang teaches the pixel according to claim 1, further comprising a fifth transistor (T3_2 in Fig. 2B) connected between the first node ( first node directly connecting transistor T6 and capacitor C2_1 in Fig. 2B) and the second node (N4 in Fig. 2B), and including a gate electrode (gate electrode of transistor T3_2 in Fig. 2B) electrically connected to a third scan line (SL2i in Fig. 2B; note that paragraph [0014] of applicant’s specification and applicant’s claim 9 discloses the third scan line is a scan line identical to the second scan line).
As to claim 8, Kang teaches the pixel according to claim 2, wherein the sixth transistor (T6 in Fig. 2B) is directed connected to the first electrode of the first capacitor (C2_1 in Fig. 2B).
As to claim 9, Kang teaches the pixel according to claim 8, wherein the third scan line (SL2i in Fig. 2B) is a scan line identical to the second scan line (SL2i in Fig. 2B;[0076];[0090];[0092]).
Claim(s) 1-2, and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2013/0002633 A1).
As to claim 1, Chung teaches a pixel ([0067]: pixel) comprising: a first transistor (M4 in Fig. 5) including a gate electrode connected to a first node (N2 in Fig. 5), a first electrode (first electrode of transistor M4 in Fig. 5) electrically connected to a first power line (ELVDD in Fig. 5;[0082]) configured to supply first driving power ([0082]: first power ELVDD), and a second electrode (second electrode of transistor M4 in Fig. 5) connected to a second node (node directly connecting OLED and M6 in Fig. 5);
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a second transistor (M1 in Fig. 5) including a first electrode (first electrode of transistor M1 in Fig. 5) electrically connected to a data line (Dm line in Fig. 5), and a gate electrode (gate electrode of transistor M1 in Fig. 5) electrically connected to a first scan line (S2n line in Fig. 5); a third transistor (M3 in Fig. 5) connected between the data line (Dm line in Fig. 5) and a third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and including a gate electrode (gate electrode of transistor M3 in Fig. 5) electrically connected to a second scan line (S1n line in Fig. 5) which is different from the first scan line (S2n line in Fig. 5), the third transistor (M3 in Fig. 5) being directly connected to the data line (Dm line in Fig. 5); a fourth transistor (M6 in Fig. 5) connected between the second node (node directly connecting OLED and M6 in Fig. 5) and the third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and including a gate electrode (gate electrode of transistor M6 in Fig. 5) electrically connected to an emission control line (En line in Fig. 5);
a sixth transistor (M2 in Fig. 5) connected between the first node (N2 in Fig. 5) and the third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and including a gate electrode (gate electrode of transistor M2 in Fig. 5) electrically connected to the second scan line (S1n line in Fig. 5), a first electrode (first electrode of transistor M2 in Fig. 5) directly connected to the first node (N2 in Fig. 5) and a second electrode (second electrode of transistor M2 in Fig. 5) directly connected to the third node (node directly connecting transistor M2 and data line Dm in Fig. 5),
a first capacitor (C2 in Fig. 5) including a first electrode connected to the second electrode of the second transistor (M1 in Fig. 5) and a second electrode connected to the first node (N2 in Fig. 5); a second capacitor (C1 in Fig. 5) connected between the first power line (ELVDD in Fig. 5) and the first node (N2 in Fig. 5); and a light emitting element (OLED in Fig. 5) connected between the third node (node directly connecting transistor M2 and data line Dm in Fig. 5) and a second power line (ELVSS in Fig. 5) configured to supply second driving power ([0066]: power ELVSS).
As to claim 2, Chung teaches the pixel according to claim 1, further comprising a fifth transistor (M5 in Fig. 5) connected between the first node (N2 in Fig. 5) and the second node (node directly connecting OLED and M6 in Fig. 5), and including a gate electrode (gate electrode of transistor M5 in Fig. 5) electrically connected to a third scan line (S1n line in Fig. 5; note that paragraph [0014] of applicant’s specification and applicant’s claim 9 discloses the third scan line is a scan line identical to the second scan line).
As to claim 8, Chung teaches the pixel according to claim 2, further comprising the sixth transistor (M2 in Fig. 5) is directed connected to the first electrode of the first capacitor (C2 in Fig. 5)
As to claim 9, Chung teaches the pixel according to claim 8, wherein the third scan line (S1n line in Fig. 5) is a scan line identical to the second scan line (S1n line in Fig. 5;[0081];[0083]).
Claim(s) 14-15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Chung (US 2013/0002633 A1).
As to claim 14, Chung teaches a display device (Abstract: display) comprising pixels connected to first scan lines, second scan lines, third scan lines, data lines, and emission control lines ([0067]: pixels 240; Fig. 5 shows pixel 240 connected to first scan line S2n, second scan line S1n directly connected to transistor M3, third scan line S1n directly connected to transistor M5 (note that paragraph [0014] of applicant’s specification discloses the third scan line is a scan line identical to the second scan line), data line Dm , and emission control lines En), wherein a pixel disposed in an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more) ([0067]; Fig. 4 shows pixel 240 disposed in an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more)) comprises:
a first transistor (M4 in Fig. 5) including a gate electrode connected to a first node (N2 directly connected to gate electrode of transistor M4 in Fig. 5) and, a first electrode electrically connected to a first power line (ELVDD in Fig. 5;[0082]) configured to supply first driving power ([0082]: first power ELVDD) and a second electrode connected to a second node (node directly connecting OLED and M6 in Fig. 5);
a second transistor (M1 in Fig. 5) including a first electrode directly connected to a j-th data line (Dm line in Fig. 5) and a second electrode (second electrode of transistor M1 in Fig. 5), and configured to be turned on in response to a first scan signal supplied from an i-th first scan line (S2n line in Fig. 5;[0079]);
a third transistor (M3 in Fig. 5) connected between the j-th data line (Dm in Fig. 5) and a third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and configured to be turned on in response to a second scan signal supplied from an i-th second scan line (S1n line in Fig. 5;[0081]), the third transistor (M3 in Fig. 5) being directly connected to the j-th data line (Dm line in Fig. 5);
a fourth transistor (M6 in Fig. 5) connected between the second node (node directly connecting OLED and M6 in Fig. 5) and the third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and configured to be turned off in response to an emission control signal supplied from a k-th emission control line (where k is an integer of 0 or more) (En line in Fig. 5;[0084]);
a sixth transistor (M2 in Fig. 5) connected between the first node (N2 in Fig. 5) and the third node (node directly connecting transistor M2 and data line Dm in Fig. 5), and including a gate electrode (gate electrode of transistor M2 in Fig. 5) electrically connected to the second scan line (S1n line in Fig. 5), a first electrode (first electrode of transistor M2 in Fig. 5) directly connected to the first node (N2 in Fig. 5) and a second electrode (second electrode of transistor M2 in Fig. 5) directly connected to the third node (node directly connecting transistor M2 and data line Dm in Fig. 5),
a first capacitor (C2 in Fig. 5) including a first electrode connected to the second electrode of the second transistor (M1 in Fig. 5) and the first node (N2 directly connected to gate electrode of transistor M4 in Fig. 5);
a second capacitor (C1 in Fig. 5) connected between the first power line (ELVDD line in Fig. 5) and the first node (N2 directly connected to gate electrode of transistor M4 in Fig. 5); and
a light emitting element (OLED in Fig. 5) connected between the third node (node directly connecting transistor M2 and data line Dm in Fig. 5) and a second power line (ELVSS in Fig. 5) configured to supply second driving power ([0066]: power ELVSS).
As to claim 15, Chung teaches the display device according to claim 14, wherein the pixel disposed in the i-th pixel row and the j-th pixel column (Fig. 4 shows pixel 240 disposed in the i-th pixel row and the j-th pixel column) further comprises: a fifth transistor (M5 in Fig. 5) connected between the first node (N2 directly connected to gate electrode of transistor M4 in Fig. 5) and the second node (node directly connecting OLED and M6 in Fig. 5), and configured to be turned on in response to a third scan signal supplied from an i-th third scan line (third scan line S1n directly connected to transistor M5 in Fig. 5 (note that paragraph [0014] of applicant’s specification discloses the third scan line is a scan line identical to the second scan line).
As to claim 18, Chung teaches the display device according to claim 14, wherein the sixth transistor (M2 in Fig. 5) is directly connected to the first electrode of the first capacitor (C2 in Fig. 5), and wherein the pixel disposed in the i-th pixel row and the j-th pixel column (Fig. 4 shows pixel 240 disposed in the i-th pixel row and the j-th pixel column) further comprises: a fifth transistor (M5 in Fig. 5) connected between the first node (N2 directly connected to gate electrode of transistor M4 in Fig. 5) and the second node (node directly connecting OLED and M6 in Fig. 5), and configured to be turned on in response to a third scan signal supplied from an i-th third scan line (third scan line S1n directly connected to transistor M5 in Fig. 5 (note that paragraph [0014] of applicant’s specification discloses the third scan line is a scan line identical to the second scan line).
Claim(s) 14-15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Kwon (US 2009/0051628 A1).
As to claim 14, Kwon teaches a display device ([0017]: display) comprising pixels connected to first scan lines, second scan lines, third scan lines, data lines, and emission control lines ([0034]; plurality of pixels 140 in Fig. 2; Fig. 4 shows pixel 140’ connected to first scan line CLn, second scan line Sn, third scan line Sn-1, data line Dm , and emission control line En), wherein a pixel disposed in an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more) ([0034]; Fig. 2 shows pixel 140 disposed in an i-th pixel row (i is an integer of 0 or more) and a j-th pixel column (j is an integer of 0 or more)) comprises:
a first transistor (M2’ in Fig. 4) including a gate electrode connected to a first node (node B in Fig. 4) and, a first electrode electrically connected to a first power line (ELVDD in Fig. 4) configured to supply first driving power ([0064]: first power supply ELVDD) and a second electrode connected to a second node (node directly connecting OLED and transistor M3’ in Fig. 4);
a second transistor (M4’ in Fig. 4) including a first electrode directly connected to a j-th data line (Dm line in Fig. 4) and a second electrode (second electrode of transistor M4’ in Fig. 4), and configured to be turned on in response to a first scan signal supplied from an i-th first scan line (CLn line in Fig. 4);
a third transistor (M1’ in Fig. 4) connected between the j-th data line (Dm in Fig. 4) and a third node (node directly connecting transistors M3’ and M5’ in Fig. 4), and configured to be turned on in response to a second scan signal supplied from an i-th second scan line (Sn line in Fig. 4), the third transistor (M1’ in Fig. 4) being directly connected to the j-th data line (Dm line in Fig. 4);
a fourth transistor (M3’ in Fig. 4) connected between the second node (node directly connecting OLED and transistor M3’ in Fig. 4) and the third node (node directly connecting transistors M3’ and M5’ in Fig. 4), and configured to be turned off in response to an emission control signal supplied from a k-th emission control line (where k is an integer of 0 or more) (En line in Fig. 4);
a sixth transistor (M5’ in Fig. 4) connected between the first node (B node in Fig. 4) and the third node (node directly connecting transistors M3’ and M5’ in Fig. 4), and including a gate electrode (gate electrode of transistor M5’ in Fig. 4) electrically connected to the second scan line (Sn line in Fig. 4),
a first electrode (first electrode of transistor M5’ in Fig. 4) directly connected to the first node (node B in Fig. 4) and a second electrode (second electrode of transistor M5’ in Fig. 4) directly connected to the third node (node directly connecting transistors M3’ and M5’ in Fig. 4),
a first capacitor (C2’ in Fig. 4) including a first electrode connected to the second electrode of the second transistor (M4’ in Fig. 4) and the first node (node B in Fig. 4);
a second capacitor (C1’ in Fig. 4) connected between the first power line (ELVDD line in Fig. 4) and the first node (node B in Fig. 4); and
a light emitting element (OLED in Fig. 4) connected between the third node (node directly connecting transistors M3’ and M5’ in Fig. 4), and a second power line (ELVSS in Fig. 4) configured to supply second driving power ([0066]: power supply ELVSS).
As to claim 15, Kwon teaches the display device according to claim 14, wherein the pixel disposed in the i-th pixel row and the j-th pixel column (Fig. 2 shows pixel 140’ disposed in an i-th pixel row and a j-th pixel column) further comprises:
a fifth transistor (M7’ in Fig. 4) connected between the first node (B node in Fig. 4) and the second node (node directly connecting OLED and transistor M3’ in Fig. 4), and configured to be turned on in response to a third scan signal supplied from an i-th third scan line (Sn-1 line in Fig. 4).
As to claim 18, Kwon teaches the display device according to claim 14, wherein the sixth transistor (M5’ in Fig. 4) is directly connected to the first electrode of the first capacitor(C2’ in Fig. 4), and wherein the pixel disposed in the i-th pixel row and the j-th pixel column (Fig. 2 shows pixel 140’ disposed in an i-th pixel row and a j-th pixel column) further comprises:
a fifth transistor (M7’ in Fig. 4) connected between the first node (B node in Fig. 4) and the second node (node directly connecting OLED and transistor M3’ in Fig. 4), and configured to be turned on in response to a third scan signal supplied from an i-th third scan line (Sn-1 line in Fig. 4).
Allowable Subject Matter
Claims 4-7, 10-13, 16-17 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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