DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the first dielectric layer and the second dielectric layer" in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, “The semiconductor structure of claim 1” in line 1 is interpreted as “The semiconductor structure of claim 5.” Accordingly, claims 7-8 and 11 are rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ikeda (US Patent No.: 11,121,135 B1, hereinafter, “Ikeda”).
Regarding claim 1, Ikeda discloses a semiconductor structure (see Ikeda, FIG. 4), comprising:
a polysilicon layer (154, col 5 and lines 27-28) having a first surface (top) and a second surface (bottom) opposite to the first surface (top, FIG. 4);
a substrate (50. FIG. 4) disposed on the second surface (bottom) of the polysilicon layer (154);
a plurality of bit line structures (152, col 4 and line 19) disposed on the substrate (50); and
a spacer structure (170+172, FIG. 4) disposed on lateral sidewalls of the bit line structure (152, FIG. 4),
wherein in a cross-sectional view perspective, the polysilicon layer (154) includes a pair of dielectric liners (170, FIG. 4) disposed in the polysilicon layer (FIGs. 4 and 5A) and disposed on lateral sidewalls of the spacer structure (170+172 for 152), and the dielectric liners (170) are spaced apart from each other and face toward each other (FIG. 4).
Regarding claim 2, Ikeda discloses the semiconductor structure of claim 1, wherein the bit line structure (152) penetrates through the polysilicon layer (154, FIG. 5A) and protrudes from the first surface (top) of the polysilicon layer (154, FIG. 5A).
Regarding claim 12, Ikeda discloses the semiconductor structure of claim 1, wherein the pair of dielectric liners (170) is disposed between one of the bit line structures (152) and an adjacent one of the bit line structures (another 152, FIG. 4).
Regarding claim 13, Ikeda discloses the semiconductor structure of claim 12, wherein the dielectric liners (170) are disposed to penetrate the polysilicon layer (154, FIG. 5A).
Allowable Subject Matter
Claims 3-5, 9-10, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-8 and 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 3, in particular, a pair of recessed portions are formed on a top surface of the substrate and one of the bit line structures is disposed between the pair of recessed portions. Claim 4 depends upon claim 3.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 5, in particular, the spacer structure includes a first dielectric layer and a second dielectric layer, wherein the second dielectric layer includes spacer portions of a dielectric layer, wherein one of the spacer portions is disposed in the polysilicon layer, and another of the spacer portions is disposed outside the polysilicon layer. Claims 6-11 depend upon claim 5.
Note: for the purpose of examination, “The semiconductor structure of claim 1” in line 1 of claim 6 is interpreted as “The semiconductor structure of claim 5.” Accordingly, claims 7-8 are rejected.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 14, in particular, a top surface of the dielectric liner is substantially coplanar with the first surface of the polysilicon layer, and a bottom surface of the dielectric liner is substantially coplanar with the second surface of the polysilicon layer. Claim 15 depends upon claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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/XIA L CROSS/ Primary Examiner, Art Unit 2892
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