DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-11, drawn to a semiconductor structure in the reply filed on 06/22/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh US 5,891,773 in view of Miida US 2004/0196685.
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Saitoh US 5,891,773
Regarding claim 1, Saitoh in Fig. 7 and col. 4, line 2-col. 5, line 31 discloses a semiconductor memory device, comprising:
a semiconductor substrate 1 with a first conductivity type col. 4, line 8; and
a plurality of transistor structures col. 5, lines 25-27 disposed on the semiconductor substrate 1, each of the transistor structures comprising:
a semiconductor layer 3 with the first conductivity type col. 4, lines 20-25;
a first floating gate 5 col. 4, lines 36-47 covering a first sidewall of the semiconductor layer 3 and having a curved sidewall opposite to the first sidewall Fig. 4, col. 4, lines 37-48;
a first tunnel oxide layer 4, Fig. 3, col. 4, lines 33-36 and col. 5, lines 25-31 formed between the first floating gate 5 and the semiconductor substrate 1, and between the first floating gate 5 and the semiconductor layer 3;
a first control gate 9 disposed on the first floating gate 5 col. 4, line 61-col. 5, line 14; and
an inter-gate dielectric layer 8 col. 4, lines 56-60 formed between the first control gate 9 and the first floating gate 5 and conformably covering the curved sidewall of the first floating gate 5.
Saitoh does not expressly disclose the concentration of the semiconductor substrate 1 having the first doping concentration with a first conductivity type; and the semiconductor layer 3 having a second doping concentration with the first conductivity type, wherein the second doping concentration is different than the first doping concentration.
However, Miida et al. in Fig. 1 and [0078] teach a semiconductor memory device 10 that increases effective writing speed that includes a semiconductor substrate 12b silicon substrate, having the first doping concentration p+ with a first conductivity type; and a semiconductor layer 12a having a second doping concentration p with the first conductivity type, wherein the second doping concentration is different than the first doping concentration (note that p+ symbolizes a higher concentration of p-type dopants than p).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Miida et al. in the semiconductor memory device of Saitoh for the purpose of increasing the effective writing speed.
Regarding claim 2, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 1. Saitoh in Fig. 7 teach wherein each of the transistor structures further comprises:
a first source/drain region 7 and a second source/drain region 6 formed in the semiconductor substrate 1 and the semiconductor layer 3, respectively, and having a second conductivity type different than the first conductivity type col. 4, lines 49-55 (e.g. arsenic is a n-type dopant), wherein the first source/drain region 7 is formed adjacent to the curved sidewall of the first floating gate 5, and the second source/drain region 6 is formed between the first floating gate and the second floating gate 5.
Regarding claim 3, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 1. Saitoh in col. 4, lines 20-25 and col. wherein the first conductivity type is P-type, and the second conductivity type is N-type col. 4, lines 49-55.
Regarding claim 4, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 3. Miida et al. in Fig. 1 and [0078] teach wherein the second doping concentration 12a is less than the first doping concentration 12b but do not teach wherein the second doping concentration is greater than the first doping concentration. Notwithstanding, one of ordinary skill in the art would have been led to the recited concentration through routine experimentation and optimization. Applicant has not disclosed that the relative concentrations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another concentration. Indeed, it has been held that mere concentration limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 5, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 3. Miida et al. in Fig. 1 and [0078] teach wherein the second doping concentration 12a is less than the first doping concentration 12b.
Regarding claim 8, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 1. Saitoh in Fig. 7 (annotated above) teaches wherein each of the transistor structures further comprises:
a second floating gate 5 covering a second sidewall of the semiconductor layer 3 opposite to the first sidewall, and having a curved sidewall opposite to the second sidewall;
a second control gate 9 disposed on the second floating gate 5, wherein the inter-gate dielectric layer 8 is formed between the second control gate 9 and the second floating gate 5 and conformally covers the curved sidewall of the second floating gate 5; and
a second tunnel oxide layer 4 formed between the second floating gate 5 and the semiconductor substrate 1 and between the second floating gate 5 and the semiconductor layer 3.
Regarding claim 9, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 8. Saitoh in Fig. 7 (annotated above) teaches wherein each of the transistor structures further comprises:
a third source/drain region 7 formed in the semiconductor substrate 1 and having a second conductivity type different than the first conductivity type, wherein the third source/drain region 7 is formed adjacent to the curved sidewall of the second floating gate 5.
Claim(s) 6, 7 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh in view of Miida et al. as applied to claims 1 and 8 above, and further in view of Wang et al. US 6,300,658.
Regarding claim 6, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 1, but do not expressly teach wherein each of the transistor structures further comprises:
a first conductive capping layer disposed on the first control gate; and
a first insulating capping layer disposed on the first conductive capping layer.
Wang et al. in Figs. 4E-4J and col. 3, line 53-col. 4, line 52 teach a semiconductor memory device wherein each transistor structure includes a first conductive capping layer 414 disposed on a first control gate 412; and a first insulating capping layer 416 disposed on the first conductive capping layer 414. Wang et al. further teach that the layer 414 is a nickel silicide and because nickel silicide has higher conductivity than conventional tungsten silicide, a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wang et al. in the memory device of Saitoh and Miida et al. for the purpose of improving the device performance.
Regarding claim 7, Saitoh in view of Miida et al. and further in view of Wang et al. teach the semiconductor memory device as claimed in claim 6. Wang et al. in col. 3, line 53-col. 4, line 52 teach wherein the first control gate comprises polysilicon, and the first conductive capping layer comprises metal or metal silicide.
Regarding claim 11, Saitoh in view of Miida et al. teach the semiconductor memory device as claimed in claim 8, but do not expressly teach wherein each of the transistor structures further comprises:
a second conductive capping layer disposed on the second control gate; and
a second insulating capping layer disposed on the second conductive capping layer.
Wang et al. in Figs. 4E-4J and col. 3, line 53-col. 4, line 52 teach a semiconductor memory device wherein each transistor structure includes a first conductive capping layer 414 disposed on a first control gate 412; and a first insulating capping layer 416 disposed on the first conductive capping layer 414. Wang et al. further teach that the layer 414 is a nickel silicide and because nickel silicide has higher conductivity than conventional tungsten silicide, a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Wang et al. in the memory device of Saitoh and Miida et al. for the purpose of improving the device performance.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims:
a sidewall protection structure formed on two opposite sidewalls of the first control gate and two opposite sidewalls of the second control gate, and extends to upper surfaces of the semiconductor substrate and the semiconductor layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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