DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koide (U.S. Patent Publication No. 2006/0056162).
Regarding claim 1, in Figures 2, 3, 6, 8, and 12, Koide discloses a method of manufacturing a wiring substrate, the method including: laminating an insulating layer (30, Figure 2) on a wiring layer (20, Figure 2); forming an opening portion (31, Figure 3) that passes through the insulating layer to the wiring layer by performing laser beam machining (paragraph [0056]); roughening a part of a surface of the insulating layer (30a, Figure 6) including an inner wall surface of the opening portion (paragraph [0056]); forming an electric conductor film (21, Figure 8) on the surface of the insulating layer; and removing an unneeded portion of the electric conductor film by performing etching (part of the seed layer 21 exposed after removing mask 51 is further removed by etching, paragraph [0070]; Figures 11 – 12).
Regarding claim 2, Koide discloses wherein the forming the opening portion includes forming the opening portion and changing properties of the part of the surface of the insulating layer including the inner wall surface of the opening portion by irradiating the insulating layer with a laser (paragraph [0056]), and the roughening includes roughening a part of the surface of the insulating layer in which the properties are changed by a desmear process performed by using a chemical solution (paragraph [0056]).
Regarding claim 3, Koide discloses wherein the roughening includes forming a mask (50, Figure 9) on the surface of the insulating layer excluding the part, and roughening the part by performing micro etching on the surface of the insulating layer by performing a dry desmear process that uses plasma (paragraph [0056]), and removing the mask (Figures 11 – 12).
Regarding claim 4, Koide discloses wherein the forming the electric conductor film includes: forming a first electric conductor film (20, Figures 1 - 2) on the surface of the insulating layer, the inner wall surface of the opening portion and a surface of the wiring layer that is exposed from the opening portion (Figure 3); forming a resist layer (40, Figure 4) on the first electric conductor film such that a portion of the first electric conductor film around the opening portion and on the inner wall of the opening portion is exposed; forming a second electric conductor film (21, Figure 8) on the portion of the first electric conductor film exposed from the resist layer; and removing the resist layer (Figures 4 – 6), and the removing the unneeded portion includes removing an unneeded portion of the first electric conductor film that is exposed from the second electric conductor film (Figure 12).
Regarding claim 5, Koide discloses wherein the first electric conductor film is formed by performing electroless plating or sputtering (paragraph [0051]), and the second electric conductor film is formed by performing electrolytic plating using power feeding from the first electric conductor film (paragraph [0066]).
Regarding claim 6, Koide discloses wherein the removing the unneeded portion of the first electric conductor film includes locating a side surface of the first electric conductor film farther inward than a side surface of the second electric conductor film Figure 12).
Regarding claim 7, Koide discloses wherein the forming the electric conductor film includes forming a connection terminal (220, Figure 11) that is connected to the wiring layer and protrudes from the opening portion by filling the electric conductor film in the opening portion (Figure 11).
Regarding claim 8, Koide discloses wherein the forming the electric conductor film includes forming a via (220, Figure 11) that connects another wiring layer that is formed on the insulating layer to the wiring layer by filling the electric conductor film in the opening portion (Figure 11).
Regarding claim 9, Koide discloses wherein the roughening includes forming a roughened portion (30a, Figure 6) on the inner wall surface of the opening portion and on the surface of the insulating layer around the opening portion, and the roughened portion has surface roughness that is 1.5 to 50 times larger than surface roughness of the surface of the insulating layer other than the roughened portion (paragraph [0064]; Figure 7).
Regarding claim 10, Koide discloses wherein the forming the opening portion includes changing properties of the inner wall surface of the opening portion and the surface of the insulating layer around the opening portion by irradiating the insulating layer with a laser (paragraph [0056]) such that temperatures of the inner wall surface of the opening portion and the surface of the insulating layer around the opening portion is higher than a glass transition temperature of a resin that constitutes the insulating layer, and the roughening includes roughening the inner wall surface of the opening portion and the surface of the insulating layer around the opening portion in which the properties are changed such that the inner wall surface of the opening portion and the surface of the insulating layer around the opening portion have surface roughness that is greater than surface roughness of a portion of the insulating layer in which the properties are not changed (paragraph [0056]; Figure 7).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847