DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 17 and 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0164019 A1 (Yang) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Yang discloses, referring primarily to figure 3, a printed circuit board comprising: a first insulating layer (110); a first metal layer (120) disposed on an upper side of the first insulating layer; a second metal layer (140) disposed on a lower side of the first insulating layer; and a first via layer (130) penetrating through at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape (132) with a width becoming narrower toward a top of the first insulating layer, and an upper surface of the first metal layer is substantially flat, and a side surface of the first metal layer has a curved surface ([0039]-[0044]) [claim 1], wherein the side surface of the first metal layer has the curved surface such that an upper width (d3) of the first metal layer is narrowest and a lower width (d2) of the first metal layer is widest ([0039]-[0044]) [claim 2], wherein the first metal layer, the first via layer, and the second metal layer respectively include a first metal (130, 150) disposed at respective boundaries of the first metal layer, the first via layer and the second metal layer with the first insulating layer [claim 3], wherein the first metal extends along the respective boundaries of the first metal layer, the first via layer and the second metal layer with the first insulating layer and is integrally provided ([0048], [0058]) [claim 4] wherein the first metal layer, the first via layer, and the second metal layer include a second metal disposed on the first metal, wherein the second metal extends to and is integrally configured with the first metal layer, the first via layer, and the second metal layer ([0053]) [claim 5], wherein respective central axes of the first metal layer, the first via layer, and the second metal layer are substantially identical ([0039]-[0044]) [claim 6], wherein the first metal layer includes a plurality of patterns, wherein heights of the plurality of patterns are substantially the same as each other ([0051]) [claim 7], wherein a width (d4) of a lower surface of the first metal layer is wider than a width (d5) of an upper surface of the first via [claim 8].
Similarly, Yang discloses, a printed circuit board comprising: a first insulating layer (110); a first metal layer (120) disposed on an upper side of the first insulating layer; a second metal layer (140) disposed on a lower side of the first insulating layer; and a first via layer (130) penetrating through at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape with a width becoming narrower toward the first metal layer, and the first metal layer, the first via layer, and the second metal layer respectively include a first metal (150, 133) disposed at respective boundaries with the first insulating layer, and a second metal disposed on the first metal ([0048], [0058]) [claim 17], wherein a width (d4) of a lower surface of the first metal layer is wider than a width (d6) of an upper surface of the first via [claim 18].
Claim(s) 1-6, 10-15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2013/0314886 A1 (Kobayashi).
Kobayashi discloses, referring primarily to figure 7, a printed circuit board comprising: a first insulating layer (11); a first metal layer (114) disposed on an upper side of the first insulating layer; a second metal layer (12) disposed on a lower side of the first insulating layer; and a first via layer (13) penetrating through at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape with a width becoming narrower toward a top of the first insulating layer, and an upper surface (114D) of the first metal layer is substantially flat, and a side surface (114E) of the first metal layer has a curved surface ([0062]) [claim 1], wherein the side surface of the first metal layer has the curved surface such that an upper width of the first metal layer is narrowest and a lower width of the first metal layer is widest ([0064]) [claim 2], wherein the first metal layer, the first via layer, and the second metal layer respectively include a first metal (not shown, referred to; [0056], [0100]) disposed at respective boundaries of the first metal layer, the first via layer and the second metal layer with the first insulating layer [claim 3], wherein the first metal extends along the respective boundaries of the first metal layer, the first via layer and the second metal layer with the first insulating layer and is integrally provided ([0056], [0100]) [claim 4] wherein the first metal layer, the first via layer, and the second metal layer include a second metal disposed on the first metal, wherein the second metal extends to and is integrally configured with the first metal layer, the first via layer, and the second metal layer ([0056], [0100]) [claim 5], wherein respective central axes of the first metal layer, the first via layer, and the second metal layer are substantially identical [claim 6], further comprising (referring primarily to figure 8): a second insulating layer (311A) disposed on a lower surface of the first insulating layer and burying the second metal layer; a third metal layer (312A) disposed on or within the second insulating layer; and a second via layer (313A) penetrating through at least a portion of the second insulating layer [claim 10].
Similarly, Kobayashi discloses, referring primarily to figures 6A-6J, a method of manufacturing a printed circuit board, comprising: forming a first barrier layer (220) on a carrier substrate (210); forming a second barrier layer (230) on the first barrier layer; forming a first insulating layer (11) on the second barrier layer; forming a first through-hole (13) penetrating through the first insulating layer; forming a second through-hole (230A) penetrating through the second barrier layer; forming a first metal layer (114) to fill the second through-hole; forming a first via layer (13) to fill the first through-hole; forming a second metal layer (12) on the first insulating layer; and removing the carrier substrate (figure 6H), the first barrier layer (figure 6I) and the second barrier layer (figure 6J) [claim 11], wherein the forming the second through-hole penetrating through the second barrier layer is performed by penetrating through the second barrier layer to connect upper and lower surfaces of the second barrier layer to each other (figure 6C) [claim 12], wherein the forming the first metal layer, the first via layer, and the second metal layer is performed by forming a first metal along outer surfaces of the first through-hole and the second through-hole and forming a second metal on the first metal ([0056], [0100]) [claim 13], wherein the forming the first metal is performed by electroless plating, and the forming the second metal is performed by electrolytic plating ([0056], [0100]) [claim 14], wherein the first metal layer, the first via layer, and the second metal layer are integrated (figure 6J) [claim 15].
Additionally, Kobayashi discloses, a printed circuit board comprising: a first insulating layer (11); a first metal layer (114) disposed on an upper side of the first insulating layer; a second metal layer (12) disposed on a lower side of the first insulating layer; and a first via layer (13) penetrating through at least a portion of the first insulating layer to connect the first metal layer to the second metal layer, wherein the first via layer has a tapered shape with a width becoming narrower toward the first metal layer, and the first metal layer, the first via layer, and the second metal layer respectively include a first metal disposed at respective boundaries with the first insulating layer, and a second metal disposed on the first metal ([0056], [0100]) [claim 17], wherein a width of a lower surface of the first metal layer is wider than a width of an upper surface of the first via [claim 18], further comprising: a second insulating layer (311A) disposed on a lower surface of the first insulating layer and burying the second metal layer; a third metal layer (312A) disposed on or within the second insulating layer; and a second via layer penetrating through at least a portion of the second insulating layer (313A) [claim 19], wherein a lower surface of the second metal layer, from which the second via extends, includes a portion spaced apart from the first metal (figure 8) [claim 20].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi in view of US 2001/0037896 A1 (Asai).
Regarding claim 9, Kobayashi discloses the claimed invention as described above with respect to claim 1 except Kobayashi does not specifically disclose that an upper surface of the first insulating layer is substantially flat, and roughness of a lower surface of the first metal layer is substantially the same as roughness of an upper surface of the second metal layer [claim 9]. However, such mating surface roughness is known in the art as evidenced by Asai ([0112]). Therefore, it would have been obvious, to one having ordinary skill in the art, to incorporate the claimed features into the invention of Kobayashi as is known in the art an evidenced by Asai. The motivation for doing so would have been to improve adhesion between the layers.
Regarding claim 16, Kobayashi discloses the claimed invention as described above with respect to claim 11 including that forming the second through-hole is performed by an etching process ([0093]-[0095]). Kobayashi does not specifically state that the forming the first through-hole is performed by a drilling process [claim 16]. However, it is well known in the art to use a drilling process to form a hole as evidenced by Asai ([0075]). Therefore, it would have been obvious, to one having ordinary skill in the art, to use the claimed drilling process in the invention of Kobayashi as is known in the art and evidenced by Asai. The motivation for doing so would have been to use a know process for precise hole formation.
Conclusion
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JEREMY C. NORRIS
Examiner
Art Unit 2847
/JEREMY C NORRIS/Primary Examiner, Art Unit 2847