Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendments filed on 7/2/2026 have been fully considered and made of record in this application.
Response to Arguments
Applicant's arguments with respect to claims 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5-7, 9, 10, 13-15, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Chang et al. (US 11,670,597).
With respect to Claims 1, 9, and 15, Chang teaches a first fan out redistribution layer 131 on a first carrier 121. A first semiconductor die 101 disposed on a first side, in a direction, of the first fan out redistribution layer 131 and coupled to a first face of the first fan out redistribution layer. Bonding a second carrier 151 to a second redistribution layer 157,159. Debonding the first carrier from the first redistribution layer 131.
A second semiconductor die 137a or 137b disposed on a second side, in the direction, of the first fan out redistribution layer 131, different from the first side, and coupled to a
second face of the first fan out redistribution layer, different from the first face. The semiconductor die 137a, 137b is at least partially encased by a second mold layer 143. The mold layer 143 being ground to expose a surface of the second semiconductor die (see col. 3 lines 5-67, col. 4 lines 1-67, col. 5 lines 1-67, and col. 6 lines 1-67; Figs. 1E – 1J).
With respect to Claims 2, Chang teaches a second fan out redistribution layer 157, 159, wherein the second fan out redistribution layer is disposed on an opposite side, in the direction, of the first semiconductor die 101 than a side on which the first fan out redistribution layer is disposed (see Fig. 1I – 1J).
With respect to Claims 5, 13, and 18, Chang teaches a plurality of solder bumps 165 coupled to the second fan out redistribution layer 157, 159, wherein the plurality of solder bumps 220 is disposed on an opposite side, in the direction, of the second fan out redistribution layer than a side on which the first semiconductor die is disposed (see
Fig. 1I – 1J).
With respect to Claim 6, Chang teaches the first semiconductor die 101 and the
second semiconductor die 137a, 137b are electrically coupled to the first fan out redistribution layer without use of a through silicon via 220 (see Figs. 1I -1J).
With respect to Claims 7 and 14, Chang teaches the first semiconductor die is
encased by a first mold layer 125. The second semiconductor die 137a, 137b is encased by a second mold layer 143 different from the first mold layer (see Figs. 1I – 1J).
With respect to Claim 10, Chang teaches a second redistribution layer 157, 159
, wherein the first semiconductor die 101 is disposed between, in a direction, the first redistribution layer and the second redistribution layer (see Figs 1I – 1J).
With respect to Claim 19, Chang teaches after encasing the second semiconductor die 137a, 137b in a second mold compound. Debonding the second carrier from the second redistribution layer (see Figs. 1G – 1J)
With respect to Claim 20, Chang teaches grinding the second mold compound 143 to expose a surface of the second semiconductor die (see col. 7 lines 55-65; Figs. 1I – 1K).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 4, 8, 11, 12, 16, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 11,670,597) as applied to claims 1 above, and further in view of Jeng et al. (US 11,239,194).
With respect to Claims 3, 11, and 21, Chang discloses the claimed invention except for the first fan out redistribution layer (i.e. the center RDL) is electrically coupled to the second fan out redistribution layer via a plurality of conducting through-package posts. However, Jeng discloses the first fan out redistribution layer (i.e. the center RDL) is electrically coupled to the second fan out redistribution layer (i.e. located at R1) via a plurality of conducting through-package posts 190 (see Figs. 1K and 1L). Thus, Chang and Jeng have substantially the same environment of a first chip between a plurality of RDL, wherein the first chip is encapsulated. Therefore, one skilled in the art before the effective filing date of the claimed invention would readily recognize incorporating a plurality of conducting through posts in the package of Chang, since the plurality of through posts would facilitate in an additional electrical connection between the first and second chips to an external device as evident by Jeng.
With respect to Claim 4, Jeng discloses the first die 140 is encased by a mold compound 160 . The plurality of conducting through package posts 190 extend through the mold compound see Figs. 1K and 1L).
With respect to Claim 8, Jeng discloses a second fan out redistribution layer (i.e. located at R1), wherein the first fan out redistribution layer is electrically coupled to the second fan out redistribution layer via a plurality of conducting through-package posts 190 disposed in the first mold layer. The second mold layer in package 300 does not include conducting through-package posts (see Fig. 1L).
With respect to Claim 12, Jeng discloses the first redistribution layer is electrically coupled to the second redistribution layer (i.e. located at R1) via a plurality of conducting through-package posts 190 (see Fig. 1L).
With respect to Claim 16, Jeng discloses the first redistribution layer includes a plurality of pillars 130 extending away from the first face of the first redistribution layer. Forming the second redistribution layer (i.e. located at R1) on the first mold compound (i.e. located in package 200). The second redistribution layer including a second plurality of electrical traces electrically coupled to the first plurality of electrical traces via the plurality of pillars (see Fig. 1L).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/Septermber 13, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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