Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 5 and 8-10 rejected under 35 U.S.C. 103 as being unpatentable over Sano (U.S. Patent Pub. No. 2016/0322374), in view of Kim (U.S. Patent Pub. No. 2022/0139831).
Regarding Claim 1
FIG. 14 of Sano discloses a semiconductor device comprising: a first gate structure including a plurality of first conductive layers (46E-46F) that are alternately stacked with a plurality of first insulating layers (32); a second gate structure including a plurality of second conductive layers (46C-46D) that are alternately stacked with a plurality of second insulating layers; a third gate structure including a plurality of third conductive layers (46A-46B) that are alternately stacked with a plurality of third insulating layers; and a first contact plug (66A) extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first (bottom contact pad) of the plurality of first conductive layers.
Sano is silent with respect to “the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure”.
FIG. 3 of Kim discloses a similar semiconductor device, wherein the first contact plug (136) including a first inflection portion located at an interface between the second gate structure (LS) and the third gate structure (LS).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sano, as taught by Kim. The ordinary artisan would have been motivated to modify Sano in the above manner for purpose of providing a semiconductor device which may improve integration density and reliability ([0004] of Kim).
Regarding Claim 2
FIG. 3 of Kim discloses the first contact plug comprises: a first sub-contact plug extending into the first gate structure through the second gate structure and connected to the first of the plurality of first conductive layers; and a second sub-contact plug connected to the first sub-contact plug through the third gate structure; wherein a width of the first sub-contact plug is different from a width of the second sub-contact plug at the first inflection portion; and wherein the first inflection portion is formed at an interface where the first sub-contact plug and the second sub-contact plug meet.
Regarding Claim 5
FIG. 14 of Sano discloses a plurality of second contact plugs (66C, 66D) extending into the second gate structure through the third gate structure, wherein each of the plurality of second contact plugs is connected to a different one of the plurality of second conductive layers.
Regarding Claim 8
FIG. 14 of Sano discloses a plurality of third contact plugs(66E, 66F) located in the third gate structure, wherein each of the plurality of third contact plugs is connected to a different one of the plurality of third conductive layers.
Regarding Claim 9
FIG. 3 of Kim discloses at least one channel structure (81) extending through the third gate structure, the second gate structure, and the first gate structure, wherein the at least one channel structure includes a second inflection portion located at an interface between the first gate structure and the second gate structure and a third inflection portion located at an interface between the second gate structure and the third gate structure.
Regarding Claim 10
FIG. 3 of Kim discloses the first inflection portion includes a step in a sidewall at an interface between consecutive sections of the first contact plug.
Claims 3, 4, 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Sano and Kim, in view of Fukuda (U.S. Patent No. 2017/0256588).
Regarding Claim 3
Sano as modified by Kim discloses Claim1, wherein the first contact plug comprises: a first sub-contact plug located in the first gate structure and the second gate structure, wherein; and a second sub-contact plug connected to the first sub-contact plug and extending through the third gate structure.
Sano as modified by Kim is silent with respect to “the first sub-contact plug includes a first pad located in the first gate structure and extends into the first gate structure through the first pad and connected to the first of the plurality of first conductive layers”.
FIG. 5 of Fukuda discloses a similar semiconductor device, wherein the first sub-contact plug includes a first pad (Z1b) located in the first gate structure and extends into the first gate structure through the first pad and connected to the first of the plurality of first conductive layers.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Fukuda. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of increasing capacity ([0005] of Fukuda).
Regarding Claim 4
FIG. 5 of Fukuda discloses the first pad protrudes from sidewalls of the first sub-contact plug.
Regarding Claim 6
Modified Sano discloses each of the plurality of second contact plugs includes a second pad located in the second gate structure and extends into the second gate structure through the second pad.
Regarding Claim 7
Modified Sano discloses the second pad protrudes from sidewalls of the second contact plug.
Claims 11-17 rejected under 35 U.S.C. 103 as being unpatentable over Sano, in view of Fukuda (U.S. Patent No. 2017/0256588).
Regarding Claim 11
FIG. 14 of Sano discloses a semiconductor device comprising: a first gate structure including a plurality of first conductive layers (46E-46F) that are alternately stacked with a plurality of first insulating layers (32); a second gate structure including a plurality of second conductive layers (46C-46D) that are alternately stacked with a plurality of second insulating layers; a third gate structure including a plurality of third conductive layers (46A-46B) that are alternately stacked with a plurality of third insulating layers; and a first contact plug (66A) extending into the first gate structure through the third gate structure and the second gate structure, wherein each of the plurality of first contact plugs is connected to a different one of the plurality of first conductive layers; and each of the plurality of second contact plugs is connected to a different one of the plurality of second conductive layers.
Sano is silent with respect to “each of the plurality of first contact plugs includes a first pad located in the first gate structure, extends into the first gate structure through the first pad”.
FIG. 13 of Fukuda discloses a similar semiconductor device, wherein each of the plurality of first contact plugs includes a first pad located in the first gate structure, extends into the first gate structure through the first pad.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Fukuda. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of increasing capacity ([0005] of Fukuda).
Regarding Claim 12
FIG. 13 of Fukuda discloses the second pad protrudes from sidewalls of the second contact plug.
Regarding Claim 13
FIG. 5 of Fukuda discloses the first pad protrudes from sidewalls of at least one of the plurality of first contact plugs.
Regarding Claim 14
FIG. 14 of Sano discloses a third gate structure including a plurality of third conductive layers (46A-46B) that are alternately stacked with a plurality of third insulating layers; and a first contact plug (66A) extending into the first gate structure through the third gate structure and the second gate structure, wherein each of the plurality of third contact plugs is connected to a different one of the plurality of the third conductive layers.
Regarding Claim 15
FIG. 5 of Fukuda discloses each of the plurality of second contact plugs includes a second pad located in the second gate structure, extends into the second gate structure through the second pad, and is connected to a different one of the plurality of second conductive layers.
Regarding Claim 16
Modified Sano discloses the second pad overlaps with an uppermost second conductive layer of the plurality of second conductive layers.
Regarding Claim 17
Modified Sano discloses the second pad protrudes from sidewalls of the second contact plug.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Sano and Fukuda, in view of Kim (U.S. Patent Pub. No. 2022/0139831).
Regarding Claim 18
Sano as modified by Fukuda discloses Claim14.
Sano as modified by Fukuda is silent with respect to “the first contact plug includes an inflection portion located at an interface between the second gate structure and the third gate structure”.
FIG. 3 of Kim discloses a similar semiconductor device, wherein the first contact plug (136) including a first inflection portion located at an interface between the second gate structure (LS) and the third gate structure (LS).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Sano, as taught by Kim. The ordinary artisan would have been motivated to modify Sano in the above manner for purpose of providing a semiconductor device which may improve integration density and reliability ([0004] of Kim).
Pertinent Art
Mori (U.S. Patent Pub. No. 2018/0277596), Yamashita (U.S. Patent Pub. No. 2019/0279996), Lee (U.S. Patent Pub. No. 2023/0223345) and Kim (U.S. Patent Pub. No. 2023/0061301).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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