Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Oath/Declaration
Oath/Declaration filed on 4/18/24 has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leong (U.S. Patent Publication No. 2019/0068181) in view of Sharma et al. (U.S. Patent Publication No. 2022/0416777)
Referring to figures 1-8, Leong teaches transistor device, comprising:
a substrate (114);
an epitaxial layer stack (106/108) formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region (110) of the transistor device (see figure 3);
a source terminal (122) electrically connected to a source region of the epitaxial layer stack;
a drain terminal (124) electrically connected to a drain region of the epitaxial layer stack;
a gate terminal (118/120) electrically connected to a gate structure laterally between the source region and the drain region (see figure 3);
a substrate terminal electrically connected to the substrate (114, see figure 3-4); and
a capacitive voltage divider circuit electrically connected between the source region and the substrate, wherein in a blocking state of the transistor device (312/314, see figures 2-4).
However, the reference does not clearly teach the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value.
Sharma et al. teaches the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value (see paragraphs# 35, 43, see figures 1a, 2c), the capacitive voltage divider circuit further comprises a capacitor in parallel with the voltage clamp device (see figures 1-2, meeting claim 9), the capacitive voltage divider circuit comprises a capacitor electrically connected between the substrate and the source region (see figures 1-2, meeting claim 10).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value in Leong as taught by Sharma et al. because it is known in the art to maintaining the substrate at a desired positive potential during blocking.
Claim(s) 2, 4, 6-9, 11-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leong (U.S. Patent Publication No. 2019/0068181) in view of Sharma et al. (U.S. Patent Publication No. 2022/0416777) as applied to claims 1, 10, further in view of Iman et al. (U.S. Patent No. 11,862,630).
Referring to figures 1-8, Leong teaches transistor device, comprising:
a substrate(114); an epitaxial layer stack (106/108) formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region (110) of the transistor device (see figure 3); a source terminal (122) electrically connected to a source region of the epitaxial layer stack; a drain terminal (124) electrically connected to a drain region of the epitaxial layer stack; a gate terminal (118/120) electrically connected to a gate structure laterally between the source region and the drain region (see figure 3); a substrate terminal electrically connected to the substrate (114, see figure 3-4); and a capacitive voltage divider circuit electrically connected between the source region and the substrate, wherein in a blocking state of the transistor device (312/314, see figures 2-4).
However, the reference does not clearly teach the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value.
Sharma et al. teaches the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value (see paragraphs# 35, 43, see figures 1a, 2c); the capacitive voltage divider circuit further comprises a capacitor in parallel with the voltage clamp device (see figures 1-2, meeting claim 9), the voltage clamp device comprises a capacitor (meeting claim 22).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value in Leong as taught by Sharma et al. because it is known in the art to maintaining the substrate at a desired positive potential during blocking.
However, the reference does not clearly teach the capacitive voltage divider circuit comprises a voltage clamp device electrically connected from the substrate to the source region in a forward direction.
Imam et al. teaches the capacitive voltage divider circuit comprises a voltage clamp device electrically connected from the substrate to the source region in a forward direction (Sb1/Sb2, figures 1-8, meeting claim 2), the voltage clamp device comprises a chain of gated GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the gated GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the gated GaN diodes in the chain is electrically connected to the source region (Sb1/Sb2, see figures 1-8, meeting claim 4), the capacitive voltage divider circuit further comprises a discharge diode device in parallel with the voltage clamp device, and wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on (see figures 1-8, meeting claims 6, 11); the discharge diode device is a gated diode having a source electrically connected to the source region, a drain electrically connected to the substrate, and a gate electrically connected to the source of the gated diode or to the gate terminal (Q3/Q4, see figures 1-8, meeting claims 7, 12); the discharge diode device is a p-GaN diode having an anode electrically connected to the source region and a cathode electrically connected to the substrate (sees figures 10a/10b, meeting claims 8, 13, 18), the capacitive voltage divider circuit comprises a discharge diode device electrically connected from the substrate to the source region in a reverse direction, and wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on (see figures 1-8, 10, meeting claim 14), the discharge diode device is a gated diode having a source electrically connected to the source region, a drain electrically connected to the substrate, and a gate electrically connected to the source of the gated diode or to the gate terminal (see figures 1-8, 10, meeting claim 15), the capacitive voltage divider circuit further comprises a first resistor electrically connected between the gate and the source of the gated diode (see figures 1-8, 10, meeting claim 16), the capacitive voltage divider circuit further comprises a second resistor electrically connected between the drain of the gated diode and the drain region(see figures 1-8, 10, meeting claim 17), the capacitive voltage divider circuit comprises: a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on; and a voltage clamp device electrically connected between the substrate and a gate of the discharge diode device(see figures 1-8, 10, meeting claim 19), the voltage clamp device comprises a diode having an anode electrically connected to the gate of the discharge diode device and a cathode electrically connected to the substrate(see figures 4, 20, meeting claim 20), the anode of the diode and the gate of the discharge diode device are electrically connected to the gate terminal(see figures 4, 20, meeting claim 21-22).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value in Leong as taught by Iman et al. because it is known in the art to improve control of the substrate potential during switching without changing the fundamental operation of the transistor.
Claim(s) 3, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leong (U.S. Patent Publication No. 2019/0068181) in view of Sharma et al. (U.S. Patent Publication No. 2022/0416777) as applied to claims 1, 10, further in view of Iman et al. (U.S. Patent No. 11,862,630) and Kalnitsky et al. (U.S. Patent Publication No. 8,895,993).
Referring to figures 1-8, Leong teaches transistor device, comprising:
a substrate(114); an epitaxial layer stack (106/108) formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel region (110) of the transistor device (see figure 3); a source terminal (122) electrically connected to a source region of the epitaxial layer stack; a drain terminal (124) electrically connected to a drain region of the epitaxial layer stack; a gate terminal (118/120) electrically connected to a gate structure laterally between the source region and the drain region (see figure 3); a substrate terminal electrically connected to the substrate (114, see figure 3-4); and a capacitive voltage divider circuit electrically connected between the source region and the substrate, wherein in a blocking state of the transistor device (312/314, see figures 2-4).
However, the reference does not clearly teach the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value.
Sharma et al. teaches the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value (see paragraphs# 35, 43, see figures 1a, 2c); the capacitive voltage divider circuit further comprises a capacitor in parallel with the voltage clamp device (see figures 1-2, meeting claim 9), the voltage clamp device comprises a capacitor (meeting claim 22).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value in Leong as taught by Sharma et al. because it is known in the art to maintaining the substrate at a desired positive potential during blocking.
However, the reference does not clearly teach a chain of p-GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the p-GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the p-GaN diodes in the chain is electrically connected to the source region (in claims 3, 5).
Kalnitsky et al. teaches a chain of p-GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the p-GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the p-GaN diodes in the chain is electrically connected to the source region (see figure 4b).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide a chain of p-GaN diodes electrically connected in series between the substrate and the source region, wherein an anode of a first one of the p-GaN diodes in the chain is electrically connected to the substrate and a cathode of a last one of the p-GaN diodes in the chain is electrically connected to the source region in Leong as taught by Kalnitsky et al. because substitution/combination of known in the diode structures to a desired forward voltage.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leong (U.S. Patent Publication No. 2019/0068181) in view of Sharma et al. (U.S. Patent Publication No. 2022/0416777) and Iman et al. (U.S. Patent No. 11,862,630).
Referring to figures 1-8, Leong teaches a transistor device, comprising: a substrate (114); an epitaxial layer stack (106/108) formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel (110) of the transistor device (see figure 3); a source terminal (122) electrically connected to a source region of the epitaxial layer stack; a drain terminal(124) electrically connected to a drain region of the epitaxial layer stack; a gate terminal (118/120) electrically connected to a gate structure laterally between the source region and the drain region (see figure 3); a substrate terminal electrically connected to the substrate (114, see figure 3-4); and a capacitive voltage divider circuit electrically connected between the source region and the substrate (312/314, see figures 2-4).
However, the reference does not clearly teach wherein the capacitive voltage divider circuit comprises a chain of diodes electrically connected from the substrate to the source region in a forward direction and/or a capacitor electrically connected between the substrate and the source region.
Sharma et al. teaches the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value (see paragraphs# 35, 43, see figures 1a, 2c). Imam et al. teaches a chain of diodes electrically connected from the substrate to the source region in a forward direction and/or a capacitor electrically connected between the substrate and the source region (see figures 1-8).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide the capacitive voltage divider circuit is configured to clamp the electric potential of the substrate to a positive value in Leong as taught by Sharma et al. and Iman et al. because it is known in the art to improve control of substrate voltage during switching.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Leong (U.S. Patent Publication No. 2019/0068181) in view of Iman et al. (U.S. Patent No. 11,862,630).
Referring to figures 1-8, Leong teaches a transistor device, comprising: a substrate (114); an epitaxial layer stack (106/108) formed on the substrate, the epitaxial layer stack including a heterojunction between two epitaxial layers having different band gaps, the heterojunction defining a channel (110) of the transistor device (see figure 3); a source terminal (122) electrically connected to a source region of the epitaxial layer stack; a drain terminal(124) electrically connected to a drain region of the epitaxial layer stack; a gate terminal (118/120) electrically connected to a gate structure laterally between the source region and the drain region (see figure 3); a substrate terminal electrically connected to the substrate (114, see figure 3-4).
However, the reference does not clearly teach a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on.
Imam et al. teaches a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on (see figures 1-8).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide a discharge diode device electrically connected from the substrate to the source region in a reverse direction, wherein the discharge diode device is configured to discharge a negative potential on the substrate when the transistor device switches from off to on in Leong as taught by Iman et al. because it is known in the art to improve control of substrate voltage during switching.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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