DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chihara (JP2015079872; IDS).
Regarding claim 1, Chihara teaches a chip resistor (chip resistor 20; see at least figs. 4-5 and paragraphs 0014-0044) comprising:
an insulating substrate (substrate 2) having a first main surface, a first side surface, and a second side surface, the first main surface being an end surface in a thickness direction
of the chip resistor, and the first side surface and the second side surface each being an
end surface in a longitudinal direction of the chip resistor;
a first front surface electrode (one surface electrode 3) disposed on an end portion of the first main surface on a side close to the first side surface;
a second front surface electrode (other surface electrode 3) disposed on an end portion of the first main surface on a side close to the second side surface;
a resistor body (resistor 4) disposed on the first main surface and electrically connected to
the first front surface electrode and the second front surface electrode;
a protective film (first protective film 5) disposed on the resistor body to partially cover the first front surface electrode and the second front surface electrode;
a first conductive resin layer (first heat dissipation electrode 15 formed of Ag resin; see paragraph 0040) disposed to extend over the first front surface electrode (3) and the protective film (5); and
a second conductive resin layer (second heat dissipation electrode 16) disposed to extend over the second front surface electrode (3) and the protective film (5), wherein
an end of the first conductive resin layer on the side close to the second side
surface is spaced apart from an end of the second conductive resin layer on the side
close to the first side surface (see the gap between the resin layers 15, 16 in figs. 4 and 5).
Regarding claim 2, Chihara teaches the chip resistor according to claim 1, wherein the end of the first conductive resin layer (15) on the side close to the second side surface and the end of the second conductive resin layer (16) on the side close to the first side surface overlap with the resistor body in a plan view (ends of the resin layers overlap the resistor 4; see figs 4-5).
Regarding claim 7, Chihara teaches the chip resistor according to claim 1, wherein
the resistor body (4) is provided with a trimming groove (13,14), and one of the first conductive resin layer and the second conductive resin layer overlaps with the trimming groove in a plan view (the end of resin layer 15 extends beyond the groove 13; see fig. 4).
Regarding claim 8, Chihara teaches the chip resistor according to claim 7, wherein the trimming groove is displaced from a center position of the resistor body in the longitudinal
direction toward the first side surface or the second side surface (a centrally located trim groove 14 extends in same direction to the current invention; see fig. 4 of Chihara and fig. 25 of the current invention).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chihara.
Regarding claim 3, Chihara teaches the claimed invention except for a distance in the
longitudinal direction between the end of the first conductive resin layer on the side
close to the second side surface and the end of the second conductive resin layer on the
side close to the first side surface is 300 µm or more and 700 µm or less.
However, Chihara teaches that the specific distance between the first heat dissipation electrode 15 and the second heat dissipation electrode 16 being determined by taking into consideration the heat dissipation performance, insulation resistance of the chip resistor having larger coverage of the trim on the resistor body (see paragraphs 0005-0012).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to take into account the gap distance can be adjusted as needed, since heavy heat dissipation on the resistor body takes place at the trim grove and complete coverage of the groove is used to significantly enhance the heat radiation effect for the resistor device.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chihara in view of Yamamoto (WO2019116814; IDS).
Regarding claim 4, Chihara teaches the claimed invention except for the conductive resin spaced apart from an end of the first front surface electrode.
Yamamoto teaches the chip resistor (see at least fig. 1A), wherein the heat dissipation layer 15 is spaced apart from an edge of the substrate (spaced apart from the end of the first front electrode) for the purpose of increasing the contact surface between the front electrode and the plating layer.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of Yamamoto with Chihara, since providing forming the conductive resin spaced apart from the end of the front electrodes allow for increasing the connection structure between the front electrode and the plating layer, thus improving the physical structure of the chip resistor device of Chihara.
Regarding claim 6, Chihara teaches the plating layers 12, 12 (see fig. 5) to cover at least the front surface electrodes 3, 3.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the prior art does not teach or suggest the chip resistor, wherein a distance in the longitudinal direction between the end of the first conductive resin layer on the side close to the first side surface and the end of the first front surface electrode on the side close to the first side surface is 100 µm or more, a distance in the longitudinal direction between the end of the second conductive resin layer on the side close to the second side surface and the end of the second front surface electrode on the side close to the second side surface is 100 µm or more, a width of a portion of the first conductive resin layer in the longitudinal direction that is located on the first front surface electrode is 100 um or more, and a width of a portion of the second conductive resin layer in the longitudinal direction that is located on the second front surface electrode is 100 µm or more.
Conclusion
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/KYUNG S LEE/Primary Examiner, Art Unit 2831
