Listed by the USPTO as LEE, KYUNG S
Tech Center 2800 • Art Units: 2831 2832 2833
This examiner grants 87% of resolved cases
LEE, KYUNG S examines in Tech Center 2800 and Art Unit 2831. The dataset contains 1164 resolved cases and records an allowance rate of 87.2%. The median time to allowance is 752 days, giving applicants a defined timing benchmark when assessing prosecution expectations in this assignment.
Interviews correspond to an 8.3% lift in the reported data. KOA, TDK, and Rohm are the leading listed companies, showing a concentration in electronics-related applicants. HSML, Bayramoglu Law Offices, and CARRIER SHENDE AND ASSOCIATES are the leading listed firms. These organizations can help practitioners identify counsel patterns and relevant portfolio experience.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18595833 | VARISTOR MODULE AND METHOD OF MANUFACTURING A VARISTOR MODULE | Non-Final OA | TDK Electronics AG |
| 18579477 | NTC SENSOR AND METHOD OF MANUFACTURING AN NTC SENSOR | Non-Final OA | TDK Electronics AG |
| 18629453 | CHIP RESISTOR | Non-Final OA | ROHM CO., LTD. |
| 18598952 | CHIP RESISTOR | Non-Final OA | ROHM CO., LTD. |
| 18598969 | CHIP RESISTOR MODULE | Non-Final OA | ROHM CO., LTD. |
| 18688698 | PROTECTIVE ELEMENT | Non-Final OA | DEXERIALS CORPORATION |
| 18712815 | ELECTRONIC COMPONENT | Non-Final OA | KOA CORPORATION |
| 18682589 | SHUNT RESISTOR | Non-Final OA | KOA Corporation |
| 18579460 | BUILT-IN CHIP RESISTOR FOR SUBSTRATE, RESISTOR BUILT-IN MODULE, MANUFACTURING METHOD OF RESISTOR BUILT-IN MODULE, AND TRIMMING | Non-Final OA | KOA Corporation |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy87.2% of resolved applications examined by Kyung S Lee were allowed (1,164 resolved cases), compared with 72.3% across Art Unit 2831 over the last five years.
This examiner's interview lift is +8.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Kyung S Lee took 752 days on average from filing to allowance.
Kyung S Lee examines applications in Art Unit 2831 in Tech Center 2800 (Semiconductors, Circuits & Optics).
