DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 12/22/2025 Amendment.
Claims 1, 3-6, 8-11 are pending. Claims 2, 7, 12-15 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 9,430,735 to Vali et al. (hereafter Vali).
Regarding independent claim 1, Vali teaches a compute-in-memory (CIM) circuit, comprising a memory array, wherein:
the memory array comprises n1 memory blocks arranged in sequence from top to bottom, and each memory block comprises n2 rows of memory-cell rows arranged in sequence, wherein n1 ≥ 2, n2 ≥ 1 (FIG. 5A: odd memory block comprising word lines 524, and even memory block comprising word lines 526, wherein 2 ≥ 2, 4 ≥ 1);
each odd memory block and an adjacent even memory block arranged therebelow form a memory group (FIG. 5A: a memory group comprising odd and even memory blocks as shown);
each memory group comprises n2 pairs of memory-cell rows, and a k-th pair of memory cell rows in each memory group comprises a k-th memory-cell row and a (n2 + k)-th memory-cell row in the corresponding memory group, wherein 1 ≤ k ≤ n2 (FIG. 5A: e.g. first word line 5241 pairs up with first word line 5261); and
the memory array is divided into n2 memory subarrays configured to be turned on in sequence, wherein a k-th memory subarray comprises the k-th pair of memory-cell rows in each memory group (FIG. 5A: e.g. first word line 5241 and first word line 5261 make one memory subarrays, and there are four subarrays as shown. FIGS. 5A-5D show each of the four subarrays are turned on in sequence);
the CIM circuit further comprises:
multiple complementary multiplexer (MUX) groups, each complementary MUX group comprising an MUX (FIG. 5A: drivers 534, which is seen as multiplexer because it selects one of word lines 524 at a time) and a flip-flop MUX (FIG. 5A: drivers 536, which is seen as flip-flop multiplexer because it selects one of word lines 526 at a time), outputs of the MUX and outputs of the flip-flop MUX in each complementary MUX group being connected to the memory-cell rows of a memory group in a one-to-one correspondence; and
a controller (FIG. 5A: controller 530) connected to each complementary MUX group through a plurality of control lines (FIG. 5A: control lines 520 and 522), and configured to output control signals to each complementary MUX group to control the n2 memory subarrays to be turn on in turn for calculation (FIG. 5A: e.g. first word line 5241 and first word line 5261 make one memory subarrays, and there are four subarrays as shown. FIGS. 5A-5D show each of the four subarrays are turned on in sequence).
Vali teaches the k-th pair of memory cell rows in each memory group comprises a k-th memory-cell row and a (n + k)-th memory cell row in the corresponding memory group instead of (2n2 + 1 – k)-th memory cell row.
However, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that pairing up memory rows as described in Vali, or as recited in claim 1 is a matter of design choice, as long as any two memory rows are selected as a subarray for computation.
Regarding dependent claim 3, Vali teaches wherein: the outputs of the MUX in each complementary MUX group are connected to memory cell rows in an odd memory block of a memory group in a one-to-one correspondence; and the outputs of the flip-flop MUX in a corresponding complementary MUX group are connected to memory cell rows in an even memory block of a corresponding memory group in a one-to-one correspondence (see FIG. 5A).
Regarding dependent claim 4, Vali teaches wherein each complementary MUX group comprises at least N control lines, and the MUX and the flip-flop MUX in each complementary MUX group share the at least N control lines, and 2N = n2 (FIG. 5A: two control lines 520 and 522).
Regarding dependent claim 5, Vali teaches wherein the CIM circuit further comprises multiple digital- to-analog converters (DACs) or buffers, and an output of each DAC or buffer is connected to a memory-cell row of the memory array (FIG. 5A: word line drivers 534 and 536 configured to generated an apply particular voltages to the word lines responsive to data stored in the word line register 532, see 7:43-58).
Regarding dependent claim 6, Vali teaches wherein the CIM circuit further comprises multiple ADCs, and inputs of the multiple ADCs are connected to bit lines of the memory array, respectively (FIG. 4: sense circuitry 430 generating a output signal comprising a digital representation, 6:36-45).
Regarding dependent claim 8, Vali teaches wherein each memory-cell row comprises multiple memory cells (see FIG. 5A).
Regarding dependent claim 9, Vali teaches wherein, n1 is an even number (FIG. 5A: n 1 = 2).
Regarding dependent claim 10, Vali teaches wherein the n2 rows of memory-cell rows in each memory block are arranged in sequence at equal intervals (see FIG. 5A).
Regarding dependent claim 11, Vali teaches wherein the multiple memory cells are SRAM or DRAM volatile memory cells, or FLASH, RRAM, PCRAM, or MRAM non-volatile memory cells (FIG. 5A shows FLASH memory cell).
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
Applicant argues:
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Applicant further argues:
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It is not clear to Examiner what Applicant intends to emphasize in this argument. Nevertheless, Examiner clarifies her interpretation of Vali in annotated FIG. 5A below:
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Applicant also argues:
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Examiner respectfully disagrees with Applicant with this argument. Controller 530 of FIG. 5A-5D sequentially turns on each of the memory subarrays for computation. For example, FIG. 5A turns on subarray comprising word lines 1 and 5 for first computation. The result obtained FIG. 5A is then used to turn on subarray comprising word lines 2 and 6 of FIG. 5B for second computation. The result obtained from FIG. 5B is then used to turn on subarray comprising word lines 3 and 7 of FIG. 5C for third computation. The result obtained from FIG. 5C is then used to turn on subarrays comprising word lines 4 and 8 of FIG. 5D for fourth computation. The activations of word lines in each of the subarray are seen as computation because the memory array is implemented as neural network, wherein neural network performs computation based on various inputs received at word lines and weights stored in the memory cells.
Claims 1, 3-6, 8-11 maintain rejected for the reasons set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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February 17, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824