DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-11, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shafi et al. (US 2022/0367714).
Regarding claim 1, Shafi discloses a transistor, comprising:
a substrate (12, fig. 1 and paragraph 0012);
a source (32, fig. 1 and paragraph 0019), a drain (30, fig. 1 and paragraph 0019), and a drain region (region to right of gate 14 including 38, 30, fig. 1and paragraphs 0019-0021) on the substrate;
an insulating layer (20, fig. 1 and paragraphs 0015-0016) on the substrate and the drain region;
a gate on the insulating layer (14, fig. 1 and paragraph 0013);
a plurality of conductive electrodes (16, fig. 1 and paragraph 0013) arranged on a side of the insulating layer away from the substrate; and
an active integrated circuit electrically connected to the plurality of
conductive electrodes (64, fig. 1 and paragraphs 0032-0033), wherein
the active integrated circuit is configured to adjust switching characteristics of
the transistor by controlling the plurality of conductive electrodes in a process of
switching the transistor from a first switching state to a second switching state, the
first switching state is an ON state and the second switching state is an OFF state,
or the first switching state is an OFF state and the second switching state is an ON
state (paragraphs 0032-0033).
Regarding claim 2, Shafi further discloses wherein to adjust the switching
characteristics of the transistor by controlling the plurality of conductive electrodes,
the active integrated circuit is further configured to:
control the plurality of conductive electrodes to deplete charge carriers in the
drain region in the OFF state to increase a breakdown voltage of the transistor, and
to accumulate the charge carriers in the drain region in the ON state to reduce an
on-resistance of the transistor (paragraphs 0032-0033).
Regarding claim 8, Shafi further discloses wherein the active integrated circuit is
embedded in the transistor to form an embedded active integrated circuit (fig. 1).
Regarding claim 9, Shafi further discloses wherein the active integrated circuit is
electrically connected to the source, the drain and the gate, and is configured to
control the source, the drain and the gate (fig. 1 and paragraphs 0032-0033).
Regarding claim 10, Shafi further discloses a plurality of external terminals electrically connected to the active integrated
circuit, wherein the plurality of external terminals included: an external source terminal, an external drain terminal and an external gate terminal, and plurality of external
terminals is configured to respectively control the source, the drain and the gate via
the active integrated circuit (fig. 1).
Regarding claim 11, Shafi further discloses wherein the active integrated circuit
includes at least one of a metal oxide semiconductor field effect transistor
(MOSFET), a bipolar transistor, or a junction field effect transistor (paragraphs 0035-0036).
Regarding claim 13, Shafi further discloses a body region on a side of the drain region on the substrate away from the drain, the source being arranged in the body region; and
a body pole in the body region and is electrically connected to the active
integrated circuit (fig. 1).
Regarding claim 14, Shafi further discloses wherein the transistor is a power
MOSFET (paragraphs 0035-0036, 0068).
Regarding claim 15, Shafi discloses a control method for a transistor, comprising:
providing a transistor including:
a substrate (12, fig. 1 and paragraph 0012);
a source (32, fig. 1 and paragraph 0019), a drain (30, fig. 1 and paragraph 0019), and a drain region (region to right of gate 14 including 38, 30, fig. 1and paragraphs 0019-0021) on the substrate;
an insulating layer (20, fig. 1 and paragraphs 0015-0016) on the substrate and the drain region;
a gate on the insulating layer (14, fig. 1 and paragraph 0013);
a plurality of conductive electrodes (16, fig. 1 and paragraph 0013) arranged on a side of the insulating layer away from the substrate; and
an active integrated circuit electrically connected to the plurality of
conductive electrodes (64, fig. 1 and paragraphs 0032-0033), controlling, by
the active integrated circuit the plurality of conductive electrodes to adjust switching characteristics of the transistor in a process of
switching the transistor from a first switching state to a second switching state, the
first switching state is an ON state and the second switching state is an OFF state,
or the first switching state is an OFF state and the second switching state is an ON
state (paragraphs 0032-0033).
Regarding claim 20, Shafi discloses an electronic device (10, fig. 1 and paragraph 0012) comprising a transistor, comprising:
a substrate (12, fig. 1 and paragraph 0012);
a source (32, fig. 1 and paragraph 0019), a drain (30, fig. 1 and paragraph 0019), and a drain region (region to right of gate 14 including 38, 30, fig. 1and paragraphs 0019-0021) on the substrate;
an insulating layer (20, fig. 1 and paragraphs 0015-0016) on the substrate and the drain region;
a gate on the insulating layer (14, fig. 1 and paragraph 0013);
a plurality of conductive electrodes (16, fig. 1 and paragraph 0013) arranged on a side of the insulating layer away from the substrate; and
an active integrated circuit electrically connected to the plurality of
conductive electrodes (64, fig. 1 and paragraphs 0032-0033), wherein
the active integrated circuit is configured to adjust switching characteristics of
the transistor by controlling the plurality of conductive electrodes in a process of
switching the transistor from a first switching state to a second switching state, the
first switching state is an ON state and the second switching state is an OFF state,
or the first switching state is an OFF state and the second switching state is an ON
state (paragraphs 0032-0033).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-7, 12 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shafi et al. (US 2022/0367714) in view of Kawahigashi (US 2007/0103458).
Regarding claim 3, Shafi discloses the transistor according to claim 1 as mentioned above. Shafi further discloses wherein the active integrated circuit (64, fig. 1) independently controls the plurality of conductive electrodes (16, fig. 1 and paragraphs 0032-0033, 0060) to adjust the switching
characteristics of the transistor by controlling the plurality of conductive electrodes. Shafi does not explicitly disclose wherein the active integrated circuit is further configured to:
adjust the switching characteristics of the transistor by turning on or off at
least one conductive electrode in an adjustable delay manner.
Kawahigashi discloses a driving integrated circuit which incorporates a plurality of divided gate electrodes provided in a transistor with a delay unit shifting ON/OFF timings to alter the switching characteristics (Abstract, figs. 1-4 and paragraphs 0034-0044). It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate Kawahigashi’s delay unit into Shafi’s device since Kawahigashi explicitly discloses the advantages of the delay units switching characteristics vs non-delayed switching transistor (see Kawahigashi figs. 3-4 vs. fig. 11 and paragraphs 0034-0044).
Regarding claim 4, Kawahigashi further discloses wherein to adjust the switching
characteristics of the transistor by controlling the plurality of conductive electrodes,
the active integrated circuit is further configured to:
turn on the at least one conductive electrode in the adjustable delay manner
following turning on the gate in a process of switching the transistor from the OFF
state to the ON state; or
turn off the gate before turning off the at least one conductive electrode in the
adjustable delay manner in a process of switching the transistor from the ON state to
the OFF state (figs. 1-3 and paragraphs 0034-0044).
Regarding claim 5, Kawahigashi further dislcoses wherein to adjust the switching
characteristics of the transistor by controlling the plurality of conductive electrodes,
the active integrated circuit is further configured to:
sequentially turn on the plurality of conductive electrodes in the adjustable
delay manner following turning on the gate in a process of switching the transistor
from the OFF state to the ON state; or
sequentially turn off the plurality of conductive electrodes in the adjustable
delay manner before turning of the gate in a process of switching the transistor from
the ON state to the OFF state (figs. 1-3 and paragraphs 0034-0044).
Regarding claim 6, Kawahigashi further discloses wherein the active integrated circuit is further configured to:
sequentially turn on the plurality of conductive electrodes in the adjustable
delay manner after turning on the gate and following a predetermined turn-on delay
in a process of switching the transistor from the OFF state to the ON state; or
turn off the gate following a predetermined turn-off delay after sequentially
turning off the plurality of conductive electrodes in the adjustable delay manner in a
process of switching the transistor from the ON state to the OFF state (figs. 1-3 and paragraphs 0034-0044).
Regarding claim 7, Kawahigashi further dislcoses wherein the active integrated circuit is further configured to:
adjust a delay time in the adjustable delay manner of the at least one
conductive electrode (figs. 1-3 and paragraphs 0034-0044).
Regarding claim 12, Kawahigashi further discloses wherein the active integrated circuit includes a switch module and a delay module;
the switch module is electrically connected to the delay module, wherein
the switch module is configured to control the ON and OFF of each of the
plurality of conductive electrodes, and
the delay module is configured to control a delay time in the adjustable delay
manner of at least one conductive electrode (figs. 1-3 and paragraphs 0034-0044).
Regarding claim 16, Shafi discloses the method according to claim 15 as mentioned above. Shafi further discloses wherein the active integrated circuit (64, fig. 1) independently controls the plurality of conductive electrodes (16, fig. 1 and paragraphs 0032-0033, 0060) to adjust the switching
characteristics of the transistor by controlling the plurality of conductive electrodes. Shafi does not explicitly disclose wherein the active integrated circuit is further configured to:
adjust the switching characteristics of the transistor by turning on or off at
least one conductive electrode in an adjustable delay manner.
Kawahigashi discloses a driving integrated circuit which incorporates a plurality of divided gate electrodes provided in a transistor with a delay unit shifting ON/OFF timings to alter the switching characteristics (Abstract, figs. 1-4 and paragraphs 0034-0044). It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate Kawahigashi’s delay unit into Shafi’s device since Kawahigashi explicitly discloses the advantages of the delay units switching characteristics vs non-delayed switching transistor (see Kawahigashi figs. 3-4 vs. fig. 11 and paragraphs 0034-0044).
Regarding claim 17, Kawahigashi further discloses wherein the adjusting of the switching characteristics of the transistor by turning on or off at least one conductive electrode in an adjustable delay manner includes:
turning on the at least one conductive electrode in the adjustable delay
manner following turning on the gate in a process of switching the transistor from the
OFF state to the ON state; or
turning off the gate before turning off the at least one conductive electrode in
the adjustable delay manner in a process of switching the transistor from the ON
state to the OFF state (see Kawahigashi figs. 3-4 vs. fig. 11 and paragraphs 0034-0044).
Regarding claim 18, Kawahigashi further discloses wherein the adjusting of the switching characteristics of the transistor by turning on or off at least one conductive electrode in an adjustable delay manner includes:
sequentially turning on the plurality of conductive electrodes in the adjustable
delay manner following turning on the gate in a process of switching the transistor
from the OFF state to the ON state; or
turning off the gate before sequentially turning off the plurality of conductive
electrodes in the adjustable delay manner in a process of switching the transistor
from the ON state to the OFF state (see Kawahigashi figs. 3-4 vs. fig. 11 and paragraphs 0034-0044).
Regarding claim 19, Kawahigashi further discloses wherein the adjusting of the switching characteristics of the transistor by turning on or off at least one conductive electrode in an adjustable delay manner includes:
sequentially turning on the plurality of conductive electrodes in the adjustable
delay manner after turning on the gate and following a predetermined turn-on delay
in a process of switching the transistor from the OFF state to the ON state; or
turning off the gate following a predetermined turn-off delay after sequentially
turning off the plurality of conductive electrodes in the adjustable delay manner in a
process of switching the transistor from the ON state to the OFF state (see Kawahigashi figs. 3-4 vs. fig. 11 and paragraphs 0034-0044).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 5966036 discloses a system with a delay circuit. US Patent 10700193 discloses a power device with multiple gate electrodes for altering switching characteristics.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 9/5/26
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