DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/06/2025 and 04/08/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8, 11-12, 15-16 & 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ladhani et al. (US 20210194434 A1), hereinafter called Ladhani.
Regarding claim 1:
Ladhani discloses in Figs. 1-4, a Doherty power amplifier (module 400), comprising:
a power splitter (power splitter 100 or 410) including a power splitter input terminal (413), a first power splitter output terminal (432) having a first output impedance, and a second power splitter output terminal (433) having a second output impedance that is different from the first output impedance,
wherein the power splitter (410) is an asymmetric Wilkinson power splitter ([0028], unequal-power, [0029], asymmetric embodiments of power splitter 100, 200), configured to receive a first amplified signal at the power splitter input terminal, split the first amplified signal into a carrier signal (zone 402, include main die) and a peaking signal (zone 403 include peaking die), output the carrier signal at the first power splitter output terminal, and output the peaking signal at the second power splitter output terminal;
a carrier amplifier die (main amplifier die 442) including a carrier amplifier input terminal and a carrier amplifier output terminal, wherein the carrier amplifier input terminal is electrically coupled to the first power splitter output terminal (432), and the carrier amplifier die (442) is configured to receive the carrier signal at the carrier amplifier input terminal and generate an amplified carrier signal based on the carrier signal at the carrier amplifier output terminal;
a peaking amplifier die (452) including a peaking amplifier input terminal and a peaking amplifier output terminal, wherein the peaking amplifier input terminal is electrically coupled to the second power splitter output terminal, and the peaking amplifier die (452) is configured to receive the peaking signal at the peaking amplifier input terminal and generate an amplified peaking signal based on the peaking signal at the peaking amplifier output terminal; and
a combining node (480) electrically coupled to the carrier amplifier output terminal and the peaking amplifier output terminal, wherein the combining node is configured to receive and combine the amplified carrier signal and the amplified peaking signal to produce an amplified output radio frequency signal.
Regarding claims 2 & 4:
Ladhani discloses in Figs. 1-4, the Doherty power amplifier of claim 1, wherein a power level of the peaking signal is greater than a power level of the carrier signal ([0028], asymmetric Doherty amplifier); and wherein the first output impedance is greater than the second output impedance ([0028], unequal-power, [0029], asymmetric embodiments of power splitter 100, 200).
Regarding claim 8:
Ladhani discloses in Figs. 1-4, the Doherty power amplifier of claim 1, wherein the power splitter (100) includes
a first leg between the power splitter input terminal (Fig. 1, terminal 113) and the first power splitter output terminal (terminal 132), and
a second leg between the power splitter input terminal and the second power splitter output terminal (terminal 133),
wherein the first leg includes a first inductor (inductor 123) and the second leg include a second inductor (inductor 129), and further including a balance resistor (resistor 126) coupled between a terminal of the first inductor (123) and a terminal of the second inductor (129), wherein the balance resistor is configured to provide isolation between the first power splitter output terminal and the second power splitter output terminal.
Regarding claim 11:
Ladhani discloses in Figs. 1-4, further comprising: an input terminal (406 of Fig. 4) configured to receive an input radio frequency signal; and
a driver amplifier (e.g. driver 445 as shown in Fig. 4 which includes input and output terminals) including a driver input terminal and a driver output terminal, wherein the driver amplifier is configured to receive the input radio frequency signal at the driver input terminal and output the first amplified signal at the driver output terminal.
Regarding claim 12:
Ladhani discloses in Figs. 1-4, a Doherty power amplifier, comprising: an input terminal (406 which unction as the RF input terminal for the module 400) configured to receive an input radio frequency signal;
a driver amplifier (driver 455 which includes input and output terminals) including a driver input terminal and a driver output terminal, wherein the driver amplifier is configured to receive an input radio frequency signal at the driver input terminal and output a first amplified signal at the driver output terminal;
a power splitter (410) including a power splitter input terminal (413), a first power splitter output terminal (432) having a first output impedance, and a second power splitter output terminal (433) having a second output impedance that is different from the first output impedance, wherein the power splitter is an asymmetric Wilkinson power splitter ([0028], unequal-power, [0029], asymmetric embodiments of power splitter 100, 200); a carrier amplifier die (442) including a carrier amplifier input terminal electrically coupled to the first power splitter output terminal; and a peaking amplifier die (452) including a peaking amplifier input terminal electrically coupled to the second power splitter output terminal.
Regarding claim 15:
Ladhani discloses in Figs. 1-4, an integrated passive device, comprising: a substrate (Fig. 4, substrate 440); and
a power splitter (410) on the substrate, the power splitter including a power splitter input terminal (413), a first power splitter output terminal (432) having a first output impedance, and a second power splitter output terminal (433) having a second output impedance that is different from the first output impedance, wherein the power splitter is an asymmetric Wilkinson power splitter ([0028], unequal-power, [0029], asymmetric embodiments of power splitter 100, 200) configured to receive a first signal at the power splitter input terminal, divide the first signal into a first output signal and a second output signal, output the first output signal at the first power splitter output terminal, and output the second output signal at the second power splitter output terminal.
Regarding claim 16:
Ladhani discloses in Figs. 1-4, the integrated passive device of claim 15, wherein a power level of the second output signal is greater than a power level of the first output signal ([0028], unequal-power, [0029], asymmetric embodiments of power splitter 100, 200).
Regarding claim 18:
Ladhani discloses in Figs. 1-4, the integrated passive device of claim 15, wherein the power splitter (100) includes
a first leg between the power splitter input terminal (Fig. 1, terminal 113) and the first power splitter output terminal (terminal 132), and
a second leg between the power splitter input terminal and the second power splitter output terminal (terminal 133),
wherein the first leg includes a first spiral inductor (inductor 123) on the substrate and the second leg includes a second spiral inductor (inductor 129) on the substrate, and further including a balance resistor (resistor 126) coupled between a terminal of the first spiral inductor (123) and a terminal of the second spiral inductor (129).
Claims 1-2, 4, 6-10, 15-16 & 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grebennikov (US 20200321918 A1).
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Regarding claim 1:
Grebennikov discloses in annotated Figs. 3 & 4, a Doherty power amplifier, comprising:
a power splitter (PWdiv) including a power splitter input terminal (IBP),
a first power splitter output terminal (Out1) having a first output impedance, and a second power splitter output terminal (Out2) having a second output impedance that is different from the first output impedance, wherein the power splitter is an asymmetric Wilkinson power splitter (see Abstract and [0006-0007], unequal power split, unequal Wilkinson power divider) configured to receive a first amplified signal at the power splitter input terminal, split the first amplified signal into a carrier signal and a peaking signal, output the carrier signal at the first power splitter output terminal (see, Fig. 3, Main and Peaking amplifiers), and output the peaking signal at the second power splitter output terminal;
a carrier amplifier die (Main die of Fig. 4) including a carrier amplifier input terminal and a carrier amplifier output terminal, wherein the carrier amplifier input terminal is electrically coupled to the first power splitter output terminal, and the carrier amplifier die is configured to receive the carrier signal at the carrier amplifier input terminal and generate an amplified carrier signal based on the carrier signal at the carrier amplifier output terminal;
a peaking amplifier die (Peaking die of Fig. 4) including a peaking amplifier input terminal and a peaking amplifier output terminal, wherein the peaking amplifier input terminal is electrically coupled to the second power splitter output terminal, and the peaking amplifier die is configured to receive the peaking signal at the peaking amplifier input terminal and generate an amplified peaking signal based on the peaking signal at the peaking amplifier output terminal; and
a combining node (annotated Com1) electrically coupled to the carrier amplifier output terminal and the peaking amplifier output terminal, wherein the combining node is configured to receive and combine the amplified carrier signal and the amplified peaking signal to produce an amplified output radio frequency signal.
Regarding claims 2 & 4:
Grebennikov discloses in annotated Fig. 3, the Doherty power amplifier of claim 1, wherein a power level of the peaking signal is greater than a power level of the carrier signal (see Abstract and [0006-0007], unequal power split, unequal Wilkinson power divider) and wherein the first output impedance is greater than the second output impedance(unequal power split).
Regarding claim 6 & 7:
Grebennikov discloses in annotated Fig. 3, wherein the first power splitter output terminal (Out1) is directly electrically coupled to the carrier amplifier input terminal (gate terminal of Main transistor); and wherein the second power splitter output terminal Out2) is directly electrically coupled to the peaking amplifier input terminal (gate terminal of Peaking transistor).
Regarding claim 8:
Grebennikov discloses in annotated Fig. 3, the Doherty power amplifier of claim 1, wherein the power splitter (PWdiv) includes
a first leg between the power splitter input terminal (Fig. 3, IBP) and the first power splitter output terminal (Out1), and
a second leg between the power splitter input terminal and the second power splitter output terminal (Out2),
wherein the first leg includes a first inductor (L1) and the second leg include a second inductor (L2), and further including a balance resistor (R1) coupled between a terminal of the first inductor (L1) and a terminal of the second inductor (L2), wherein the balance resistor is configured to provide isolation between the first power splitter output terminal and the second power splitter output terminal.
Regarding claim 9:
Grebennikov discloses in annotated Fig. 3, the Doherty power amplifier of claim 8, wherein the first leg includes a variable phase advance circuit (e.g. capacitor C4 and inductor L4) coupled between the terminal of the first inductor (L1) and the first power splitter output terminal (Out1).
Regarding claim 10:
Grebennikov discloses in annotated Fig. 3, the Doherty power amplifier of claim 9, wherein the second leg includes a variable phase lag circuit (e.g. capacitor 5, and inductor L5) coupled between the terminal of the second inductor (L2) and the second power splitter output terminal (Out2), wherein the variable phase advance circuit is configured differently from the variable phase lag circuit.
Regarding claim 15:
Grebennikov discloses in annotated Figs. 3 & 4, an integrated passive device, comprising: a substrate (Fig. 4, substrate and [0024]); and
a power splitter ( (PWdiv, IPD) on the substrate, the power splitter including a power splitter input terminal (IP1), a first power splitter output terminal (Out1) having a first output impedance, and a second power splitter output terminal (Out2) having a second output impedance that is different from the first output impedance, wherein the power splitter is an asymmetric Wilkinson power splitter (see Abstract and [0006-0007], unequal power split, unequal Wilkinson power divider) configured to receive a first signal at the power splitter input terminal, divide the first signal into a first output signal and a second output signal, output the first output signal at the first power splitter output terminal, and output the second output signal at the second power splitter output terminal.
Regarding claim 16:
Grebennikov discloses in annotated Figs. 3 & 4, the integrated passive device of claim 15, wherein a power level of the second output signal is greater than a power level of the first output signal (see Abstract and [0006-0007], unequal power split, unequal Wilkinson power divider).
Regarding claim 18:
Grebennikov discloses in annotated Figs. 3 & 4, the integrated passive device of claim 15, wherein the power splitter includes
a first leg between the power splitter input terminal (IBP) and the first power splitter output terminal (Out1), and
a second leg between the power splitter input terminal and the second power splitter output terminal (Out2),
wherein the first leg includes a first spiral inductor (inductor L1) on the substrate and the second leg includes a second spiral inductor (inductor L2) on the substrate, and further including a balance resistor (resistor R1) coupled between a terminal of the first spiral inductor (L1) and a terminal of the second spiral inductor (L2).
Regarding claim 19:
Grebennikov discloses in annotated Figs. 3 & 4, the integrated passive device of claim 18, wherein the first leg includes a variable phase advance circuit (e.g. capacitor C4 andL4) on the substrate coupled between the terminal of the first inductor (L1) and the first power splitter output terminal (Out1)
Regarding claim 20:
Grebennikov discloses in annotated Figs. 3 & 4, the integrated passive device of claim 19, wherein the second leg includes a variable phase lag circuit (e.g. capacitor C5 and inductor L5) coupled between the terminal of the second inductor and the second power splitter output terminal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 5, 13-14 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ladhani.
Regarding claims 3, 5, 13-14 & 17:
Ladhani discloses the limitations as applied in claim 2 except for wherein the power level of the peaking signal is from 1.6 to 2.2 times greater than the power level of the carrier signal and a volume of the peaking amplifier die is at least 1.6 times greater than a volume of the carrier amplifier die; and wherein the output impedance of the first power splitter output terminal is between 25 ohms and 35 ohms and the output impedance of the second power splitter output terminal is between 10 ohms and 20 ohms; and wherein the power level of the second output signal is from 1.6 to 2.2 times greater than the power level of the first output signal. It would have been obvious to one having ordinary skill in the art at the time the invention was made to configure or set or select the power level of the peaking signal is from 1.6 to 2.2 times greater than the power level of the carrier signal and a volume of the peaking amplifier die is at least 1.6 times greater than a volume of the carrier amplifier die; and wherein the output impedance of the first power splitter output terminal is between 25 ohms and 35 ohms and the output impedance of the second power splitter output terminal is between 10 ohms and 20 ohms; and wherein the power level of the second output signal is from 1.6 to 2.2 times greater than the power level of the first output signal, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 9-10 & 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ladhani in view of Ahmed et al. (US 20130194023 A1, hereinafter Ahmed).
Regarding claims 9, 10 & 19-20:
Ladhani discloses the limitations as applied in claim 8 except for the first leg includes a variable phase advance circuit coupled between the terminal of the first inductor and the first power splitter output terminal; and the second leg includes a variable phase lag circuit coupled between the terminal of the second inductor and the second power splitter output terminal, wherein the variable phase advance circuit is configured differently from the variable phase lag circuit.
Ahmed discloses in Fig. 2, a Doherty amplifier comprising a power divider circuit which includes negative shift 229 and positive shift 231.
Ladhani and Ahmed are analogous art because they are from the same field of endeavor, namely Doherty amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Ladhani to have added negative shift 229 and positive shift 231, as taught by Ahmed. Such a modification would have imparted the advantageous benefit of improving efficiency/linearity of the amplifier over a wider range of signal levels, see page 3, continuous paragraph [0022], lines 4-5, as taught by Ahmed to Ladhani reference, thereby suggesting the obviousness of such a modification.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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