Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 04/08/24. Claims 1-8, 10-14, 17, 19-22, and 24 and 25 are pending in this application.
Information disclosure Statement
The information disclosure statement filed on 04/08/24, 01/24/25, and 02/03/25 have been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 10-14, 17, 19-22, 24, 25 are rejected under 35 U.S.C. §102(a)(1) as being unpatentable over Yu (US 20230121734 A1).
Regarding claim 1, Yu discloses a semiconductor device, comprising: an active array in which a plurality of active patterns (105) are arranged on a substrate (Figure 3); a gate structure (126) extending in a first direction ("first direction") parallel to an upper surface of the substrate and crossing central portions of the active patterns (Figure 3); a bit line structure (150) contacting first portions of the active patterns (105) adjacent to a first sidewall of the gate structure (see fig 13, disclosing 105 adjacent to sidewalls of 150), the bit line structure extending in a second direction ("second direction") parallel to the upper surface of the substrate and perpendicular to the first direction (Figure 3); and a capacitor (240) electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure (see Figures 1, 3), wherein, in a plan view, an upper end portion of each of the active patterns (105) and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction intersecting the first direction at an oblique angle (Figure 3), and wherein the active patterns that are arranged side by side in the second direction define an active column (Figure 3). Yu further discloses 150 crosses 105 over the center portions.
Regarding claim 2, Yu discloses the semiconductor device of claim 1, wherein, in a plan view, sidewalls of each of the active patterns have one of a straight shape extending in the third direction, a curved shape extending in the third direction (see fig 23, wher3 150 has a straight portion near the bottom), and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction (see fig 23, wher3 150 has a straight portion near the bottom).
Regarding claim 3, Yu discloses the semiconductor device of claim 1, wherein the third direction corresponds to a direction along which each of the active patterns extends (see fig 23, disclosing third direction to be up).
Regarding claim 4, Yu discloses the semiconductor device of claim 1, wherein, in a plan view, the active patterns that are arranged side by side in the first direction define an active row (see fig 23, disclosing active patterns arranged alternately), wherein at least a portion of the active patterns included in an even-numbered active row is disposed between adjacent active patterns include in an odd-numbered active row(see fig 23, disclosing active patterns arranged alternately, see also fig 7 disclosing alternate arrangements).
Regarding claim 5, Yu discloses the semiconductor device of claim 1, wherein the gate structure is in a first recess on the active patterns (see fig 23, disclosing 126 in recess patterns).
Regarding claim 6, Yu discloses the semiconductor device of claim 1, wherein an upper surface of the first portion of the active pattern is lower than an upper surface of the second portion of the active pattern (see fig 23, disclosing 150 has an upper and lower portion of a u shape).
Regarding claim 7, Yu discloses the semiconductor device of claim 1, wherein an insulation spacer (see fig 150 disclosing spacers 168 in fig 23, )extends in the second direction and is defined between a sidewall of the second portion of the active pattern and a sidewall of the bit line structure (see 162 between bitline).
Regarding claim 8, Yu discloses the semiconductor device of claim 1, wherein the bit line structure includes a bit line pattern including a conductive material and a first insulation pattern (see par a[0036] disclosing 142a).
Regarding claim 10, Yu discloses the semiconductor device of claim 1, further comprising: a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the active patterns (see fig 23, 220 having contact isolating shape); and a second contact structure contacting at least a portion of the upper surface of the first contact plug, and wherein the capacitor contacts the second contact structure (see fig 23 disclosing 204 contact structure near the top).
Regarding claim 11, Yu discloses the semiconductor device of claim 10, wherein a plurality of second contact structures (see contact structures in fig 23)are arranged in a honeycomb structure disposed at each vertex of connected hexagons and a center of each of the hexagons (see honeycomb distributed structure, fig 3).
Regarding claim 12, Yu discloses the semiconductor device of claim 10, wherein an uppermost surface of the first contact plug is lower than an uppermost surface of the bit line structure (see fig 23, where 222 is recessed in 204).
Regarding claim 13, Yu discloses the semiconductor device of claim 10, further comprising a second insulation pattern between the first contact plugs in the second direction, and wherein the first contact plug and the second insulation pattern are aligned with the second direction (see fig 23, 220 aligned in the second direction).
Regarding claim 14, Yu discloses the semiconductor device of claim 1, further comprising: a contact plug contacting an upper surface of the second portion of the active pattern (see 190/192), and an upper portion of the contact plug including a recessed portion (see fig 23, disclosing 190 in a trench); a landing pad pattern contacting at least a portion of the upper surface of the contact plug (see 109/192); and a third insulation pattern filling an opening between a plurality of landing pad patterns and contacting the recessed portion (see insulation 200).
Regarding claim 19, Yu discloses a semiconductor device, comprising: an active array in which a plurality of active patterns are arranged o n a substrate (fig. 3); a gate structure 126 extending in a first direction (“first direction”) parallel to an upper surface of the substrate and crossing central portions of the active patterns 105, wherein each of the active patterns are divided into a first portion and a second portion by the gate structure (see 105 is divided by 126 in to at least two portions); a bit line structure (150) contacting the first portions of the active patterns (see fig 12, disclosing 126 contacting 150),
ii) extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction (see fig 11, disclosing bit line extending in second direction), and
iii) including a bit line pattern comprising a conductive material stacked on a first insulation pattern (see fig 12 disclosing stack 160/150); and capacitors electrically connected to second portions of the active patterns (see fig 26, disclosing capacitors 240 on top portions), respectively, wherein, in a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction intersecting the first direction at an oblique angle (see fig 26 disclosing oblique angle), and wherein an upper surface of the first portion of each of the active patterns is lower than an upper surface of the second portion of the active pattern (see fig 23, disclosing curvature of doped region 105, having at least two levels).
Regarding claim 20, Yu discloses the semiconductor device of claim 19, wherein the active patterns that are arranged side by side in the second direction define an active column (see fig 23, disclosing side by side ), and the active patterns that are arranged side by side in the first direction define an active row (see fig 23 and fig 7 disclosing array arrangement), and wherein first portions of the active patterns included in the active column are arranged in the second direction (see figs 7 and 23, disclosing 105 in array arrangement), and central portions of active patterns included in the active row are arranged in the first direction (see fig 23 disclosing 105 arranged alongside 126).
Regarding claim 21, Yu discloses the semiconductor device of claim 19, wherein, in a plan view, a plurality of active columns are repeatedly arranged in the first direction (see fig 7 and 23).
Regarding claim 22, Yu discloses the semiconductor device of claim 19, in a plan view, sidewalls of each of the active patterns have one of a straight shape extending in the third direction (see fig 23, disclosing active patterns 105 having a upward curved shape), a curved shape extending in the third direction(see fig 23, disclosing active patterns 105 having a upward curved shape), and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction(see fig 23, disclosing active patterns 105 having a upward curved shape where lower portion is trench shaped).
Regarding claim 24, Yu discloses the semiconductor device of claim 19, further comprising: a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the active patterns (see fig 23, disclosing contact plugs 202); and a second contact structure contacting at least a portion of the upper surface of the first contact plug (see 202), wherein the capacitor contacts the second contact structure (see 202/222, fig 23).
Regarding claim 25, Yu discloses a semiconductor device, comprising:
an active array in which a plurality of active patterns are arranged on a substrate (see figs 7 and 23, disclosing arrays of 105); a gate structure extending in a first direction parallel to an upper surface of the substrate and crossing central portions of the active patterns (see fig 7 , disclosing 126 crossing 105), wherein each of the active patterns are divided into a first portion and a second portion by the gate structure; a bit line structure contacting the first portions of the active patterns (see fig 12, disclosing 126 contacting 150),
ii) extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction (see fig 11, disclosing bit line extending in second direction), and
iii) including a bit line pattern comprising a conductive material stacked on a first insulation pattern stacked (see fig 12 disclosing stack 160/150);
and iii) including a bit line pattern 150 having a conductive material and a first insulation pattern stacked (see fig 23, 150 with 206); and an insulation spacer disposed between a sidewall of a second portion of the active pattern and a sidewall of the bit line structure (see 100/110 between 105 and 126), and extending in the second direction (see fig 7 disclosing 105/126 extending in second direction); first contact plugs contacting upper surfaces of second portions of the active patterns (see fig 23, 190), respectively, and each of the first contact plugs having an isolated shape (see trench shape 190); a second insulation pattern between the first contact plugs in a second direction (see 110); and a capacitor electrically connected to each of the first contact plugs (222/204).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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