Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species 3 in the reply filed on 5/19/26 is acknowledged. The traversal is on the ground(s) that species 1 and 2 are not distinct. This is not found persuasive because the best prior art was determined for the elected claims and the Xie reference does not read upon the non-elected claims thus requiring a second and third burdensome search to address the additional species. Applicant is reminded however that should future prosecution render the determination of allowable subject matter and such allowable subject matter be properly incorporated into the withdrawn claims- rejoinder may be possible.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Xie et al (US 2022/0406715)
16. (Original) A semiconductor structure comprising:
a first source/drain (S/D) region (Fig.12A/13A-13C (80/1210) and [0078]) of a first nanosheet (NS) transistor ([0022/0035]) and [0078]) and a second S/D region (Fig.12A/13A-13C (80/1210) and [0078]) of a second NS transistor ([0022/0035]);
a deep trench via (Fig.13 (C (1030) and [0074]) in a single diffusion break region between the first S/D region (Fig.12A/13A-13C (80/1210) and [0078]) and the second S/D region (Fig.12A/13A-13C (80/1210) and [0078]);
a frontside metal wire (Fig,13C (1320/1020) and [0085/0074]) conductively connected to a top surface of the deep trench via (Fig.13 (C (1030) and [0074]); and
a backside metal wire (Fig,13C (1320/1020) and [0085/0074]) conductively connected to a bottom surface of the deep trench via (Fig.13 (C (1030) and [0074]).
17. (Original) The semiconductor structure of claim 16, further comprising a metal gate (Fig.10A/13A-C (92) and [0072]) and a gate cut dielectric (Fig.10A/13A-C (50/54/52) and [0057]), wherein the deep trench via (Fig.13 (C (1030) and [0074]) is in a width direction of the metal gate (Fig.10A/13A-C (92) and [0072]) and the gate cut dielectric (Fig.10A/13A-C (50/54/52) and [0057]) insulates the metal gate (Fig.10A/13A-C (92) and [0072]) from the deep trench via (Fig.13 (C (1030) and [0074]).
18. (Original) The semiconductor structure of claim 17, wherein the frontside metal wire (Fig,13C (1320/1020) and [0085/0074]) is not vertically aligned with the backside metal wire (Fig,13C (1320/1020) and [0085/0074]) and a horizontal distance between the frontside and backside metal wires (Fig,13C (1320/1020) and [0085/0074]) is less than a length of the deep trench via(Fig.13 (C (1030) and [0074]), the length of the deep trench via (Fig.13 (C (1030) and [0074]) is along the width direction of the metal gate (Fig.10A/13A-C (92) and [0072]).
19. (Original) The semiconductor structure of claim 16, further comprising a first set of inner spacers (Fig.10A/13A-C (64/54) and [0071/0058]) between the first S/D region (Fig.12A/13A-13C (80/1210) and [0078]) and a first side of the deep trench via (Fig.13 (C (1030) and [0074]) and a second set of inner spacers (Fig.10A/13A-C (64/54) and [0071/0058]) between the second S/D region (Fig.12A/13A-13C (80/1210) and [0078]) and a second side of the deep trench via (Fig.13 (C (1030) and [0074]), the first side being opposite the second side.
20. (Original) The semiconductor structure of claim 16, further comprising a frontside via (Fig,13C (1320/1020) and [0085/0074]), a backside via (Fig,13C (1320/1020) and [0085/0074]), and a backside contact (Fig,13C (1320/1020) and [0085/0074]), wherein the frontside metal wire (Fig,13C (1320/1020) and [0085/0074]) is conductively connected to the top surface of the deep trench via (Fig.13 (C (1030) and [0074]) through the frontside via (Fig,13C (1320/1020) and [0085/0074]), and the backside metal wire (Fig,13C (1320/1020) and [0085/0074]) is conductively connected to the bottom surface of the deep trench via (Fig.13 (C (1030) and [0074]) through the backside via (Fig,13C (1320/1020) and [0085/0074])and the backside contact (Fig,13C (1320/1020) and [0085/0074]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wei et al (US 20230069107); Chu et al (US 20250253238) and Yang et al (US 20260107507) teach similar deep trench vias with front and backside contacts in nanosheet transistors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
6/27/26
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