DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/6/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant's arguments filed 2/6/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… a first switch directly connected to the first memory via the second lane of the first memory, and configured to connect the second lane of the first memory to either the second lane of the first controller or the first lane of the second controller … a micro controller directly connected to the first memory …” because:
Bai’s MUX connected to 8639 connector and not directly to the NVMe SSD;
Bai’s DUALPORTEN# is send to 8639 connector and not directly to NVMe SSD; and
Bai’s shows connection to 8639 connector and not connection between a memory and lanes, or any connection between a memory lane and a controller lane; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, the examiner is equating the claimed “… first switch …” to the combination of Bai’s 2:1 PCIe MUX and 8639 Connector’s PCIe [3:2] in Figures 3-4, which is directly coupled to PCIe interface of corresponding NVMe SSD, and the examiner is further equating the claimed “… micro controller …” to the combination of Bai’s Control Logic FPGA and 8639 Connector’s DUALPORTEN# in Figures 3-4, which is directly coupled to corresponding NVMe SSD. Additionally, Bai further teaches/suggests connecting the second lane of the first memory (e.g. associated with PCIe interface of corresponding NVMe SSD for coupling with PCIe [3:2]: [0015]) to either the second lane of the first controller (e.g. associated with lanes of 2X PCIe that interconnect CPU0 and NVMe SSD: [0015]) or the first lane of the second controller (e.g. associated with lanes of 2X PCIe that interconnect CPU1 and NVMe SSD: [0015]) (Fig. 2-5; [0014]-[0015]; [0035]-[0053]; and [0060]-[0066]).
As applicant appears to be applying the above arguments for independent claim 1 towards independent claim 11, the examiner will also apply the above response for independent claim 1 towards independent claim 11.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Long et al. (US Pub.: 2022/0283960) in view of Bai et al. (US Pub.: 2018/0246833).
As per claim 1, Long teaches/suggests a system comprising: a first portion configured to mount component(s) including first and second lanes thereto (e.g. associated with component(s) on PCIe peripheral card with corresponding PCIe lanes for communication: Fig. 2; and [0031]); a second portion including an edge configured to connect to a slot of an apparatus that includes corresponding first and second lanes and corresponding first and second lanes (e.g. associated with lanes of connector (241) being connected to PCIe slot (251) in Fig. 2; [0031]); and being mounted to the first portion,
wherein operating accordingly in a state where the edge is connected to the slot, and operating accordingly in the state where the edge is connected to the slot (Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; and [0070]).
Long does not teach the system comprising:
a first memory;
a memory evaluating apparatus that includes a first controller including interface and a second controller including interface; and
a communication controller, and configured to control communication between the first memory and the memory evaluating apparatus, wherein
the communication controller includes:
a first switch directly connected to the first memory via the second lane of the first memory configured to connect the second lane of the first memory to either the second lane of the first controller or the first lane of the second controller; and
a micro controller directly connected to the first memory, and configured to set an operation mode of the first memory to a single port or a dual port, and control the first switch,
in a case where the first memory is the single port, the communication controller is configured to control the communication such that the communication is performed between the first lane of the first memory and the first lane of the first controller, and the communication is performed between the second lane of the first memory and the second lane of the first controller, and
in a case where the first memory is the dual port, the communication controller is configured to control the communication such that the communication is performed between the first lane of the first memory and the first lane of the first controller, and the communication is performed between the second lane of the first memory and the first lane of the second controller.
Bai teaches/suggests a system comprising: a first memory (e.g. associated with NVMe SSD in Fig. 2); a memory evaluating apparatus that includes a first controller including interface (e.g. associated with CPU0 and SW0 interfacing accordingly in Fig. 3-4) and a second controller including interface (e.g. associated with CPU1 and SW1 interfacing accordingly in Fig. 3-4); and a communication controller, and configured to control communication between the first memory and the memory evaluating apparatus (e.g. associated with Control Logic FPGA and all the MUX devices including PCIe MUX controlling communication accordingly: [0065]), wherein the communication controller includes: a first switch (e.g. equate to the combination of 2:1 PCIe MUX and 8639 Connector’s PCIe [3:2] in Fig. 3-4) directly connected to the first memory via the second lane of the first memory (e.g. associated with the combination of 2:1 PCIe MUX and 8639 Connector’s PCIe [3:2] in Fig. 3-4 being directly coupled to PCIe interface of corresponding NVMe SSD) configured to connect the second lane of the first memory (e.g. associated with PCIe interface of corresponding NVMe SSD for coupling with PCIe [3:2]: [0015]) to either the second lane of the first controller (e.g. associated with lanes of 2X PCIe that interconnect CPU0 and NVMe SSD: [0015]) or the first lane of the second controller (e.g. associated with lanes of 2X PCIe that interconnect CPU1 and NVMe SSD: [0015]); and a micro controller directly connected to the first memory (e.g. equate to the combination of Control Logic FPGA and 8639 Connector’s DUALPORTEN# in Fig. 3-4 that is directly coupled to corresponding NVMe SSD), and configured to set an operation mode of the first memory to a single port or a dual port (e.g. associated with DUALPORTEN# being enabled (high=1) to configure NVMe SSD to operate in x4 mode or DUALPORTEN# being disabled (low=0) to configure NVMe SSD to operate in x2 mode: TABLE 1; [0047]-[0049]), and control the first switch (e.g. associated with Control Logic FPGA controlling using SW_SEL_0 and SW_SEL_1 in TABLE 1), in a case where the first memory is the single port, the communication controller is configured to control the communication such that the communication is performed between the first lane of the first memory and the first lane of the first controller, and the communication is performed between the second lane of the first memory and the second lane of the first controller (e.g. associated with work state W1/W5 where all lanes are communicating with CPU0: Fig. 3-4; Table 1), and in a case where the first memory is the dual port, the communication controller is configured to control the communication such that the communication is performed between the first lane of the first memory and the first lane of the first controller, and the communication is performed between the second lane of the first memory and the first lane of the second controller (e.g. associated with work state W3 where lanes are split for communicating with CPU0 and CPU1: Fig. 3-4; Table 1) (Fig. 2-5; [0014]-[0015]; [0035]-[0053]; and [0060]-[0066]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Bai’s interconnecting states into Long’s system for the benefit of dynamically partitioning PCIe disk arrays based on software configuration/policy distribution (Bai, [0014]) to obtain the invention as specified in claim 1.
As per claim 3, Long and Bai teach/suggest all the claimed features of claim 1 above, where Long and Bai further teach/suggest the board comprising wherein the micro controller is configured to set the operation mode of the first memory to the single port or the dual port by outputting a first signal to the first memory (e.g. associated with DUALPORTEN#), and control the first switch by outputting a second signal to the first switch (e.g. associated with SW_SEL_0 and SW_SEL_1) (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claim 4, Long and Bai teach/suggest all the claimed features of claim 1 above, where Long and Bai further teach/suggest the board comprising wherein the first and second controllers are provided in a single controller to which bifurcation that divides one link into two links is applicable (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]), wherein it would have been obvious and/or well-known to one of ordinary skilled in the art to implement the CPUs on a single circuit.
As per claim 5, Long and Bai teach/suggest all the claimed features of claim 1 above, where Long and Bai further teach/suggest the board comprising wherein the communication controller is further configured to control the communication between the first memory and the memory evaluating apparatus, based on a signal received from the memory evaluating apparatus (e.g. associated with management platform providing policy for configuring the communication accordingly: [0044]-[0045] and [0065] of Bai) (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claim 6, Long and Bai teach/suggest all the claimed features of claim 1 above, where Long and Bai further teach/suggest the board comprising wherein the first portion is configured to mount a second memory including first and second lanes thereto, the edge of the second portion is configured to connect to the slot of the memory evaluating apparatus that further includes a third controller including first and second lanes and a fourth controller including first and second lanes, the communication controller is further configured to control communication between the second memory and the memory evaluating apparatus, in a case where the second memory is the single port in the state where the edge is connected to the slot, the communication controller is further configured to control the communication such that the communication is performed between the first lane of the second memory and the first lane of the third controller, and the communication is performed between the second lane of the second memory and the second lane of the third controller, and in a case where the second memory is the dual port in the state where the edge is connected to the slot, the communication controller is further configured to control the communication such that the communication is performed between the first lane of the second memory and the first lane of the third controller, and the communication is performed between the first lane of the second memory and the first lane of the fourth controller (e.g. associated with implementing a second architecture with the second memory, third controller and fourth control that mirrors the first architecture with the first memory, first controller and second control) (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claim 7, Long and Bai teach/suggest all the claimed features of claim 6 above, where Long and Bai further teach/suggest the board comprising wherein the communication controller includes: the first switch configured to connect the second lane of the first memory to either the second lane of the first controller or the first lane of the second controller (e.g. associated with NVMe SSD communicate with CPU0 or communicate with CPU0 and CPU1); a second switch configured to connect the second lane of the second memory to either the second lane of the third controller or the first lane of the fourth controller (e.g. associated with duplicating the parts such that NVMe SSD communicate with CPU2 or communicate with CPU2 and CPU3: [0043]); and the micro controller configured to set the operation made of the first memory to the single port or the dual port (e.g. associated with DUALPORTEN# for CPU0 and CPU1), set an operation mode of the second memory to the single port or the dual port (e.g. associated with DUALPORTEN# for CPU2 and CPU3), and control the first and second switches (e.g. associated with SW_SEL_0 and SW_SEL_1 for CPU 0 to CPU 3) (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claim 8, Long and Bai teach/suggest all the claimed features of claim 7 above, where Long and Bai further teach/suggest the board comprising wherein the micro controller is configured to set the operation mode of the first memory to the single port or the dual port by outputting a first signal to the first memory, control the first switch by outputting a second signal to the first switch, set the operation mode of the second memory to the single port or the dual port by outputting a third signal to the second memory, and control the second switch by outputting a fourth signal to the second switch (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claim 9, Long and Bai teach/suggest all the claimed features of claim 6 above, where Long and Bai further teach/suggest the board comprising wherein the first to fourth controllers are provided in a single controller to which bifurcation that divides one link into four links is applicable (Long, Fig. 2; Fig. 6-7; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features as it would have been obvious and/or well-known to one of ordinary skilled in the art to implement the CPUs on a single circuit.
As per claim 10, Long and Bai teach/suggest all the claimed features of claim 6 above, where Long and Bai further teach/suggest the board comprising wherein the communication controller is further configured to control the communication between the first and second memories and the memory evaluating apparatus, based on a signal received from the memory evaluating apparatus (e.g. associated with management platform providing policy for configuring the communication accordingly: [0044]-[0045] and [0065] of Bai) (Long, Fig. 2; Fig. 6; [0029]-[0034]; [0045]; [0058]; [0070]; and Bai, Fig. 2-5; Fig. 2-5; [0014]-[0015]; [0035]-[0053]; [0060]-[0066]).
As per claims 11, and 13-20, claims 11, and 13-20 are rejected in accordance to the same rational and reasoning as the above rejection of claims 1, and 3-10.
II. PERTINENT RELATED PRIOR ART
Blevins et al. (US Pub.: 2019/0034372): discloses PCIe bus and connector can be divided into a number of data lanes. Each data lane can include two pairs of conductors, one for receiving and one for transmitting. A PCIe card can have one (x1), four (x4), eight (x8), or sixteen (x16) data lanes associated with a single PCIe slot. In certain examples, a first network interface controller can be directly connected with a first set of data lanes of the PCIe bus via the a first set of slot connector terminals, and a second network interface controller can be directly connected with a second set of data lanes of the PCIe bus via the a second set of slot connector terminals. The first set of data lanes can be distinct from, or not-overlapping, the second set of data lanes.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 3-11, and 13-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 March 13, 2026