DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Office Action is in response to amendments and remarks filed on 02/17/2026. Claims 1-3, 6-20 are currently pending.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites “a default mode”, line 19 and further recites “a default mode”, line 25. It is unclear if these recitations refer to the same or to different limitations.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(l) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okazaki (WO2022201839A, using US 2024/0113148 A1 as an English translation).
Regarding claim 1, Okazaki discloses an imaging device, comprising:
a semiconductor substrate (11, Fig. 1 or 130, Fig.4); and a plurality of recta shared pixels (100) disposed in the semiconductor substrate (130, Fig.1), wherein each recta (100) shared pixel includes: a first photoelectric conversion region (101, Fig.4) ; a second photoelectric conversion region (104); an intra-pixel separation structure (172), wherein the intra-pixel separation structure (172) establishes a separation barrier between the first photoelectric conversion region (101) and the second photoelectric conversion region (104, see Fig.4);
a control gate (110, Fig.4) wherein the control gate includes a control gate electrode (153), wherein the control gate electrode (153) includes a planar structure adjacent to a surface of the semiconductor substrate (130) opposite a light incident surface of the semiconductor substrate (see Fig.4, the gate electrode 153 lies near the surface, which is opposite the light incident surface)
and a vertical structure that extends from the planar structure and towards the light incident surface of the semiconductor substrate (Fig.4 and [0085], “The gate electrode 153 is partially embedded in the semiconductor substrate 130 and has a bottom and a side adjacent to the semiconductor region 145”, [0087], “connecting unit 110 can be expanded in the thickness direction of the semiconductor substrate 130 by forming the gate electrode 153 in a shape embedded in the semiconductor substrate 130”; the embedded portion of the gate electrode 153 in the thickness direction toward to the light incident surface indicates as the vertical structure), wherein the vertical structure extends between a first portion of the first photoelectric conversion region (101) and a first portion of the second photoelectric conversion region (104) (see Fig.4), and
wherein in a plan view an area of the planar structure of the control gate electrode (153) is greater than an area of the vertical structure of the control gate electrode (see Fig.4, the top surface or the flat surface of control gate electrode 153 is larger than the vertical side structures, in the plan view); and
a path (145, Fig.4) between the separation structure (172) and the control gate (110)([0086], “When the ON voltage is applied to the gate electrode 153, a channel is formed in the semiconductor region 145”),
wherein in a default mode of operation a first voltage (“When the ON voltage”, see [0086]) is supplied to the control gate to increase an effective size of the path, lowering a potential barrier between the first photoelectric conversion region and the second photoelectric conversion region ([0086]“When the ON voltage is applied to the gate electrode 153, a channel is formed in the semiconductor region 145. This channel brings the semiconductor regions 141 and 142 constituting the photoelectric conversion units 101 and 104 into a conductive state. Charges can thus move between the semiconductor regions 141 and 142”. Showing that allowing charges to move between the semiconductor regions 141 and 142 is reducing/ lowering a potential barrier)
, wherein in another mode of operation a second voltage (“a voltage of 0 V”, [0095]) is supplied to the control gate to reduce the effective size of the path, raising the potential barrier between the first photoelectric conversion region and the second photoelectric conversion region ([0095], “applying a voltage of 0 V when the MOS transistor to be controlled is turned off. a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor.”), and wherein the first voltage is higher than the second voltage (the on voltage is higher than the off voltage, see Fig. 6 and [0095], “A portion of the value “1” represents a signal of the above-described ON voltage… applying a voltage of 0 V when the MOS transistor to be controlled is turned off. a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor”).
111
Regarding claim 2, Okazaki, as discussed in claim 1, discloses the first voltage ([0095], value “1” represents ON voltage) being supplied to the control gate electrode in the default mode of operation ([0117], “prevent charge overflow…maintain the linearity of image signals), and wherein the second voltage ([0095], “a voltage of 0 V”) is supplied to the control gate electrode in the another mode of operation (“individual transfer/phase difference signal”, see [0109] “a mode for generating an image signal”, and [0122], “an image signal is generated through individual transfer or when a phase difference signal is generated… time required for signal generation can be shortened”).
Regarding claim 3, Okazaki, as discussed in claim 2, discloses a gap being present between the intra-pixel separation structure (172) and the control gate electrode (153)(see Fig.4, the intra-pixel separation structure and the control gate electrode are not continuous, they are separated by a channel is formed in the semiconductor region 145, [0086]).
Regarding claim 6, Okazaki, as discussed in claim 1, discloses the control gate electrode (153, Fig.4), further includes first and second vertical portions that extend toward the light incident surface of the semiconductor substrate (Fig.4 and [0087], “the gate electrode 153 in a shape embedded in the semiconductor substrate 130, and expanded in the thickness direction of the semiconductor substrate 130”).
Regarding claim 7, Okazaki, as discussed in claim 2, discloses (Fig.4) each recta shared pixel (100) further including: a first transfer gate (105/151), wherein the first transfer gate (105/151) selectively connects the first photoelectric conversion region (101) to a first floating diffusion (109a) ; and a second transfer gate (108), wherein the second transfer gate (108) selectively connects the second photoelectric conversion region (104) to a second floating diffusion (109b).
Regarding claim 8, Okazaki, as discussed in claim 7, discloses (Fig.4) the first transfer gate (105) including a first transfer gate electrode (151), wherein the second transfer gate (108) includes a second transfer gate electrode (152), and wherein the first and second transfer gate electrodes (151, 152) are on a same plane as the control gate electrode (153, see Fig.4).
Regarding claim 9, Okazaki, as discussed in claim 8, discloses (Fig.4) the first transfer gate (105) being a same size as the second transfer gate (108, according to Fig.4, the transfer gates have the same size).
Regarding claim 10, Okazaki, as discussed in claim 9, discloses (Fig.4) the first transfer gate (105) being a same shape as the second transfer gate (108, according to Fig. 4, the transfer gates have the same shape).
Regarding claim 11, Okazaki, as discussed in claim 10, discloses (Fig.4) the control gate (110) being a same material as the first and second transfer gates ([0078], “The gate electrodes 151 and 152 may be made of polycrystalline silicon”, the control gate 110 including the gate electrode 153 is formed from polycrystalline silicon, [0085]).
Regarding claim 12, Okazaki, as discussed in claim 11, discloses (Fig.4) planar structure of the control gate (110) being a same shape as the first and second transfer gates (105, 108).
Regarding claim 13, Okazaki, as discussed in claim 1, discloses (Fig.4) the first photoelectric conversion region (101) being a first photodiode, and wherein the second photoelectric conversion region (104) is a second photodiode ([0042], “The pixels 100 may have a share pixel structure. This pixel share structure includes a plurality of photodiodes”).
Regarding claim 14, Okazaki discloses (Fig.4) a system, comprising:
an imaging lens (194); an image sensor (100), the image sensor (100) including: a plurality of recta shared pixels disposed in an array (see Fig.5, [0090], “pixel region 3 is configured by repeatedly disposing the pixels 100 arrayed in two rows and two columns”)
, wherein each recta shared pixel (100) in the plurality of recta shared pixels (pixels 100 arrayed) includes:
a first photoelectric conversion region (101); a second photoelectric conversion region (104)
; an intra-pixel separation structure (172), wherein the intra-pixel separation structure (172) establishes a separation barrier between the first photoelectric conversion region (101) and the second photoelectric conversion region (104); and
a control gate (110) , wherein the control gate includes a control gate electrode (153)
, wherein the control gate electrode (153) includes a planar structure adjacent to a surface of a semiconductor substrate (130) opposite a light incident surface of the semiconductor substrate (see Fig.4, the gate electrode 153 lies near the surface, which is opposite the light incident surface) and
a vertical structure that extends from the planar structure and towards the imaging lens (194)(see Fig.4 and [0085], “The gate electrode 153 is partially embedded in the semiconductor substrate 130 and has a bottom and a side adjacent to the semiconductor region 145”, showing that the embedded portion of the gate electrode 153 in the thickness direction toward the imaging lens 194)
, wherein the vertical structure extends between a first portion of the first photoelectric conversion region (101) and a first portion of the second photoelectric conversion region (104), wherein in a plan view an area of the planar structure of the control gate electrode is greater than an area of the vertical structure of the control gate electrode (see Fig.4, the top surface or the flat surface of control gate electrode 153 is larger than the vertical side structures, in the plan view),
wherein the control gate (110) is disposed adjacent to the intra-pixel separation structure (172), wherein in a default mode of operation a first voltage is supplied to the control gate ([0086]“When the ON voltage is applied to the gate electrode 153) to lower an effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region ([0086]“When the ON voltage is applied to the gate electrode 153, a channel is formed in the semiconductor region 145. This channel brings the semiconductor regions 141 and 142 constituting the photoelectric conversion units 101 and 104 into a conductive state. Charges can thus move between the semiconductor regions 141 and 142”; Showing that allowing charges to move between the semiconductor regions 141 and 142 is reducing/ lowering a potential barrier),
wherein in another mode of operation a second voltage is supplied to the control gate ([0095], “applying a voltage of 0 V”) to raise the effective potential barrier between the first photoelectric conversion region and the second photoelectric conversion region ([0095], “applying a voltage of 0 V when the MOS transistor to be controlled is turned off, a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor”), and
wherein the first voltage is higher than the second voltage (the on voltage is higher than the off voltage, see Fig. 6 and [0095], “A portion of the value “1” represents a signal of the above-described ON voltage… applying a voltage of 0 V when the MOS transistor to be controlled is turned off. a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor”); and
a processor ([0253], “a processing circuit that processes the image signal generated by the image signal generating unit”, there is a processor as part of the device),
wherein in a default mode the control gate of at least some of the recta shared pixels are supplied with a first voltage and an effective potential barrier between the first and second photoelectric conversion regions of the at least some of the recta shared pixels is equal to or less than a potential barrier established by the intra-pixel separation structure alone ([0086], “[0086]
When the ON voltage is applied … Charges can thus move between the semiconductor regions 141 and 142”, indicating that the effective potential barrier is equal to or less than a potential barrier established by the intra-pixel separation structure alone since the charge moves move between the semiconductor regions 141 and 142 via the channel formed in the semiconductor region 145),
wherein in another mode of operation the control gate of the at least some of the recta shared pixels is supplied with a second voltage ([0095], “applying a voltage of 0 V when the MOS transistor to be controlled is turned off”) and the effective potential barrier between the photoelectric conversion regions is greater than the effective potential barrier between the photoelectric conversion regions when first voltage is supplied to the control gate of the at least some of the recta shared pixels ([0086] , [0095], when the gate is turn off , second voltage is applied. The channel is not formed in the semiconductor region 145, which raises the potential barrier, so the effective potential barrier between the photoelectric conversion regions is greater than the effective potential barrier between the photoelectric conversion regions when first voltage is supplied), and wherein the first voltage is higher than the second voltage (the on voltage is higher than the off voltage, see Fig. 6 and [0095], “A portion of the value “1” represents ON voltage… applying a voltage of 0 V when the MOS transistor to be controlled is turned off, a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor”).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Okazaki in view of Asahi et al. (WO 2022/201835 A1, cited in IDS).
Regarding claim 15, Okazaki discloses a method, comprising:
providing an image sensor (100, Fig.4) having a semiconductor substrate (11, Fig.1 or 130, Fig.4) and a plurality of recta shared pixels disposed in the semiconductor substrate (see, Fig.1)
wherein each recta shared pixel (100) includes: a first photoelectric conversion region (101) ;a second photoelectric conversion region (104);
an intra-pixel separation structure (172), wherein the intra-pixel separation structure establishes a separation barrier between the first photoelectric conversion region (101) and the second photoelectric conversion region (104); and
a control gate (110), wherein the control gate (110) is disposed adjacent to the intra- pixel separation structure (172), wherein the control gate includes a control gate electrode (153), wherein the control gate electrode (153) includes a planar structure adjacent to a surface of the semiconductor substrate (130) opposite a light incident surface of the semiconductor substrate (see Fig.4, the gate electrode 153 lies near the surface, which is opposite the light incident surface), and
a vertical structure that extends from the planar structure and towards the light incident surface of the semiconductor substrate (Fig.4 and [0085], “The gate electrode 153 is partially embedded in the semiconductor substrate 130 and has a bottom and a side adjacent to the semiconductor region 145”, [0087], “connecting unit 110 can be expanded in the thickness direction of the semiconductor substrate 130 by forming the gate electrode 153 in a shape embedded in the semiconductor substrate 130”; the embedded portion of the gate electrode 153 in the thickness direction toward to the light incident surface indicates as the vertical structure),
,wherein the vertical structure extends between a first portion of the first photoelectric conversion region (101) and a first portion of the second photoelectric conversion region (104), and wherein in a plan view an area of the planar structure of the control gate electrode is greater than an area of the vertical structure of the control gate electrode (see Fig.4, the top surface or the flat surface of control gate electrode 153 is larger than the vertical side structures, in the plan view);
supplying a first voltage (“ON voltage”, [0086]) to the control gate (110 comprising 153) of each recta shared pixel of the plurality of recta shared pixels (100) to lower an effective potential barrier between the first photoelectric conversion region (101) and the second photoelectric conversion region (104) of each of the recta shared pixels (100) in a default mode of operation ([0086], “When the ON voltage is applied to the gate electrode 153… Charges can thus move between the semiconductor regions 141 and 142”, allowing charges to move between the semiconductor regions 141 and 142 is reducing/ lowering a potential barrier);
supplying a second voltage ([0095], “applying a voltage of 0 V”) to the control gate of each recta shared pixel of the plurality of recta shared pixels (100) to raise the effective potential barrier between the first photoelectric conversion region (101) and the second photoelectric conversion region (104) of each of the recta shared pixels (100) in another mode of operation ([0095], “applying a voltage of 0 V when the MOS transistor to be controlled is turned off, a different voltage, for example, −1 V may also be applied to the signal voltage for turning off the MOS transistor”),
wherein the first voltage is higher than the second voltage ([0095], “A portion of the value “1” represents a signal of the above-described ON voltage… applying a voltage of 0 V when the MOS transistor to be controlled is turned off”, showing the value 1 (high) is greater than value 0 (low)),
Although Okazaki discloses an mode of operation includes a phase detection autofocus mode “phase difference signal”, [0240]; and [0117], “the photoelectric conversion unit connecting unit 110 in the pixel 100 and connects the photoelectric conversion units 101 to 104 to each other. This can prevent charge overflow even when some of the photoelectric conversion units 101 to 104 reach the saturation charge amount and can maintain the linearity of image signals with respect to the amount of incident light”, this could be imaging mode. However, if not, Asahi et al., disclose a default mode of operation includes an imaging mode (“the image signal mode”, paragraph [0129]), and wherein another mode of operation includes a phase detection autofocus mode (paragraph [ 0114], “phase difference signal mode”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okazaki, by utilizing the teaching of Asahi et al., to provide more flexible and efficient operation, getting better image quality.
Regarding claim 16, Okazaki in view of Asahi et al., as discussed in claim 15, Okazaki does not disclose the second voltage being only supplied to the control gate of each recta shared pixel of the plurality of recta shared pixels during the phase detection autofocus mode as claimed. Asahi et al., disclose the second voltage is only supplied to the control gate of each recta shared pixel of the plurality of recta shared pixels during the phase detection autofocus mode (paragraphs [0114], [0119], this is the only time the negative voltage applied during the phase difference signal mode). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okazaki, by utilizing the teaching of Asahi et al., to ensure high quality signal, reducing signal crosstalk.
Regarding claim 17, Okazaki in view of Asahi et al., as discussed in claim 15, Okazaki does not disclose the effective potential barrier in the phase detection autofocus mode of operation being greater than a potential barrier established by the intra-pixel separation structure alone as claimed. Asahi et al., disclose the effective potential barrier in the phase detection autofocus mode of operation being greater than a potential barrier established by the intra-pixel separation structure alone (paragraph [0144], “a negative gate voltage is applied to the overflow gate 109 to prevent a decrease in the potential barrier of the overflow path 108, and transfer of charges from the photoelectric conversion section 102 to the photoelectric conversion section 101 can be prevented”, indicating that in order to prevent overflow between 101 and 102, the potential barrier is increased or greater). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okazaki, by utilizing the teaching of Asahi et al., to ensure high quality signal, reducing signal crosstalk.
Regarding claim 18, Okazaki in view of Asahi et al., as discussed in claim 15, Okazaki does not disclose the effective potential barrier in the imaging mode of operation being equal to or less than a potential barrier established by the intra-pixel separation structure alone as claimed. Asahi et al., disclose the effective potential barrier in the imaging mode of operation being equal to or less than a potential barrier established by the intra-pixel separation structure alone (Fig. 6 and paragraph [0141], “a high gate voltage is applied to the overflow gate 109, and the potential barrier of the overflow path 108 becomes relatively low. Therefore, as illustrated in FIG. 6A, the charge overflowing from the photoelectric conversion section 102 is transferred to the photoelectric conversion section 101 through the overflow path 108”, indicating that the effective potential barrier is equal to or less than a potential barrier established by the intra-pixel separation structure alone since the charge moves from the photoelectric conversion section 102 to lower photoelectric conversion section 101 via the overflow path). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Okazaki, by utilizing the teaching of Asahi et al., to ensure high quality signal, reducing signal crosstalk.
Regarding claim 19, Okazaki in view of Asahi et al., as discussed in claim 15, Okazaki discloses the intra-pixel separation structure being separated from the control gate by a gap (see Fig.4, the intra-pixel separation structure and the control gate electrode are not continuous, they are separated by a channel is formed in the semiconductor region 145, [0086]).
Regarding claim 20, Okazaki in view of Asahi et al., as discussed in claim 15, Okazaki discloses the photoelectric conversion regions (101, 104, Fig.4) being photodiodes ([0042], “The pixels 100 may have a share pixel structure. This pixel share structure includes a plurality of photodiodes”).
Response to Arguments
7. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAI THI NGOC TRAN whose telephone number is (571)272- 3456. The examiner can normally be reached Monday-Friday: 9:00-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, GEORGIA EPPS can be reached on (571)272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.T.T./Examiner, Art Unit 2878
/THANH LUU/Primary Examiner, Art Unit 2878
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