DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group I, claims 1-18 in the reply filed on 7/6/2026 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1, 2 and 4-7 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Yoo et al. (US 2023/0146621).
Re claim 1, Yoo teaches, under BRI, Fig. 2 & 5F, [0025, 0031, 0035, 0086], a semiconductor package, comprising:
-a substrate (21, 23);
-a semiconductor stacked structure (110, right chip stack 120) on the substrate (21, 23), wherein the semiconductor stacked structure (110, right chip stack 120) includes a logic die (CPU chip 110) and a high-bandwidth memory (lower HMB DRAM 120) on the logic die (110);
-one or more semiconductor dies (left chip stack 120) on the substrate (21, 23) and arranged side by side with the semiconductor stacked structure (e.g., with right chip stack 120); and
-one or more surface mount devices (SMD) (top chip 120T) on the semiconductor stacked structure (110, right chip stack 120).
PNG
media_image1.png
481
859
media_image1.png
Greyscale
Re claim 2, Yoo teaches, Fig. 2, [0021], wherein: the logic die (110) comprises a plurality of first through silicon vias (113).
Re claim 4, Yoo teaches wherein: the logic die (110) [0025] comprises a central processing unit (CPU) or a graphic processing unit (GPU).
Re claim 5, Yoo teaches, under BRI, [0005], wherein the high-bandwidth memory comprises a buffer die (buffer chip) and a plurality of memory dies (memory devices) stacked on the buffer die (buffer chip).
Re claim 6, Yoo teaches, Fig. 5F, wherein: an upper memory die (120T-1) of the plurality of memory dies (120) stacked on the buffer die (buffer chip) comprises a plurality of second through silicon vias (123).
Re claim 7, Yoo teaches, Fig. 5F, wherein: the one or more surface mount devices (top 120T) are electrically connected to the plurality of second through silicon vias (123).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Lee et al. (US 2022/0293527).
The teachings of Yoo have been discussed above.
Re claim 3, Yoo does not explicitly teach wherein the logic comprises a system on chip (SoC).
Lee teaches the use of system on chip (SoC) [0029].
As taught by Lin, one of ordinary skill in the art would utilize & modify the above teaching to obtain the logic comprising a system on chip (SoC) as claimed, because it aids in achieving desired stacked structure with improved integration density.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination Yoo due to above reason.
Re claim 8, in combination cited above, Lee teaches wherein the one or more semiconductor dies comprise a power management integrated circuit (PMIC) (e.g., PMIC die) [0029].
5. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Kwon et al. (US 2011/0013353).
The teachings of Yoo have been discussed above.
Re claim 9, Yoo does not explicitly teach wherein the one or more semiconductor dies comprise a multi-bank DRAM (M-DRAM).
Kwon teaches “The at least one memory chip may include…and a multi-bank DRAM…” [0010].
As taught by Kwon, one of ordinary skill in the art would utilize & modify the above teaching to obtain the one or more semiconductor dies comprise a multi-bank DRAM (M-DRAM) as claimed, because it aids in achieving a multi-chip package structure with improved performance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination Yoo due to above reason.
6. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of Yu et al. (US 2017/0345807)
The teachings of Yoo have been discussed above.
Re claim 10, Yoo does not explicitly teach wherein: the one or more surface mount devices comprises a capacitor.
Yu teaches, Figs. 15-16, [0019], the one or more surface mount devices (40) comprises a capacitor.
As taught by Yu, one of ordinary skill in the art would utilize & modify the above teaching to obtain a capacitor as claimed, because capacitor is an essential element & aids in improving performance of the formed memory structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination Yoo due to above reason.
7. Claims 1, 2, 4-7 and 10 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2017/0345807) in view of Yoo et al. (US 2023/0146621).
Re claim 1, Yu teaches, under BRI, Fig. 16, [0018, 0028, 0030, 0042, 0043], a semiconductor package, comprising:
-a substrate (68);
-a semiconductor stacked structure (58, right 34’) on the substrate (68), wherein the semiconductor stacked structure (58, right 34’) includes a logic die (58) and a memory (right 34’, similar to 34) on the logic die (58);
-one or more semiconductor dies (left 34’) on the substrate and arranged side by side with the semiconductor stacked structure (58, right 34’) (e.g., with right 34’); and
-one or more surface mount devices (SMD) (434) on the semiconductor stacked structure (58, right 34’).
Note: alternatively, topmost 534 with passive component can be consider as SMD.
PNG
media_image2.png
526
638
media_image2.png
Greyscale
Yu does not explicitly teach a high-bandwidth memory.
Yoo teaches the use of a high-bandwidth memory (e.g., HBM DRAM 120, Fig. 2, [0031]).
As taught by Yoo, one of ordinary skill in the art would utilize & modify the above teaching to obtain a high-bandwidth memory in a stack structure as claimed, because it aids in achieving a thinned chip stack with improved speed & energy efficiency.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yoo in combination Yu due to above reason.
Re claim 2, in combination cited above, Yoo teaches, Fig. 2, [0021], wherein the logic die (110) comprises a plurality of first through silicon vias (113).
Re claim 4, Yu teaches the logic die (58) [0028] comprises a central processing unit (CPU) or a graphic processing unit (GPU).
Re claim 5, in combination cited above, Yoo teaches, [0005], wherein the high-bandwidth memory comprises a buffer die (buffer chip) and a plurality of memory dies (memory devices) stacked on the buffer die (buffer chip).
Re claim 6, in combination cited above, Yu teaches, Fig. 16, [0019, 0043], wherein an uppermost memory die (534) of the plurality of memory dies (in 34’) stacked on the buffer die (see Yoo’s teaching) comprises a plurality of second through silicon vias (42).
Re claim 7, Yu/Yoo does not explicitly teach wherein the one or more surface mount devices are electrically connected to the plurality of second through silicon vias.
Yu’s Fig. 11B teaches, [0038], the one or more surface mount devices (234) are electrically connected to the plurality of second through silicon vias (42).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Yu’s Fig. 11B to obtain the one or more surface mount devices are electrically connected to the plurality of second through silicon vias as claimed, because it aids in facilitating interconnection between upper die and external device & reducing the height of package.
Re claim 10, Yu teaches, Figs. 15-16, [0019], wherein the one or more surface mount devices comprise a capacitor (40).
8. Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu as modified by Yoo as applied to claim 1 above, and further in view of Lee et al. (US 2022/0293527).
The teachings of Yu/Yoo have been discussed above.
Re claim 3, Yu/Yoo does not explicitly teach wherein the logic comprises a system on chip (SoC).
Lee teaches the use of system on chip (SoC) [0029].
As taught by Lin, one of ordinary skill in the art would utilize & modify the above teaching to obtain the logic comprising a system on chip (SoC) as claimed, because it aids in achieving desired stacked structure with improved integration density.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lee in combination Yu/Yoo due to above reason.
Re claim 8, in combination cited above, Lee teaches wherein the one or more semiconductor dies comprise a power management integrated circuit (PMIC) (e.g., PMIC die) [0029].
9. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as modified by Yoo as applied to claim 1 above, and further in view of Kwon et al. (US 2011/0013353).
The teachings of Yu/Yoo have been discussed above.
Re claim 9, Yu/Yoo does not explicitly teach wherein the one or more semiconductor dies comprise a multi-bank DRAM (M-DRAM).
Kwon teaches “The at least one memory chip may include…and a multi-bank DRAM…” [0010].
As taught by Kwon, one of ordinary skill in the art would utilize & modify the above teaching to obtain the one or more semiconductor dies comprise a multi-bank DRAM (M-DRAM) as claimed, because it aids in achieving a multi-chip package structure with improved performance.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kwon in combination Yu/Yoo due to above reason.
10. Claims 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2023/0146621) in view of Kim et al. (US 2018/0006006).
Re claim 11, Yoo teaches, under BRI, Figs. 2 & 5F, [0025, 0031, 0035, 0086], a semiconductor package, comprising:
-a substrate (21, 23);
-a semiconductor stacked structure (110s, right chip stack 120) right on the substrate (21, 23), the semiconductor stacked structure including:
a logic die (CPU 110);
a high-bandwidth memory (two or three lower HBM DRAM 120) on the logic die (110); and
a first material (underfill 135) substantially surrounding the high-bandwidth memory (120) on the logic die (110);
one or more semiconductor dies (left chip stack 120) on the substrate (21, 23) and arranged side by side with the semiconductor stacked structure (e.g., with right chip stack 120);
one or more surface mount devices (SMD) (top chip 120T) on the semiconductor stacked structure (110, right chip stack 120); and
a second molding material (130) substantially surrounding the semiconductor stacked structure (110, right stack 120), the one or more semiconductor dies (left stack 120), and the one or more surface mount devices (120T) on the substrate (21, 23).
PNG
media_image1.png
481
859
media_image1.png
Greyscale
Yoo does not explicitly teach a first molding material.
Kim teaches, Fig. 13, [0077], the use of first & second molding materials (160, 660).
As taught by Kim, one of ordinary skill in the art would utilize & modify the above teaching into Yoo to obtain a first mold material as claimed, because it aids in enhancing protection & improving reliability of the formed package. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination Yoo due to above reason.
Re claims 12 & 13, Yoo teaches, Fig. 5F, [0032], wherein: the semiconductor stacked structure further comprises an interconnection structure (124) between the logic die (110) and the high-bandwidth memory (120); wherein the interconnect structure (124) comprises a plurality of micro bumps.
Re claim 14, Yoo teaches, Figs. 5A-C, [0021, 0029], the interconnect structure comprises a plurality of first bonding pads (112b) and a first silicon insulating layer (115) on a top surface of the logic die (110); and the interconnection structure comprises a plurality of second bonding pads (122a) and a second silicon insulating layer (125) on a bottom surface of the high-bandwidth memory (120).
Re claim 15, Yoo teaches, under BRI, Fig. 5C, wherein: each first bonding pad (112b) of the plurality of first bonding pads (112b) is directly bonded (# physically bonded) (via 124 in straight direction) to each second bonding pad (122a) of the plurality of second bonding pads (122a).
Note: in [0032], 124 may be attached.
Re claim 16, Yoo teaches, under4 BRI, Fig. 5C, wherein: the first silicon insulating layer (115) is directly bonded (# physically bonded) (via 135as in straight direction) to the second silicon insulating layer (125).
Note: in [0032], 124 may be attached.
Re claim 17, Yoo teaches, Fig. 5F, wherein: top surface of the one or more surface mount devices (SMD) (120T) is free from coverage from the second molding material (130).
Re claim 18, Yoo teaches, Fig. 5F, wherein: a top surface of the one or more semiconductor dies (left chip stack 120) is free from coverage form the second molding material (130).
11. Claims 15 and 16 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Yoo as modified by Kim as applied to claims 11, 12 & 14 above, and further in view of Yu et al. (US 2022/0262783, “Yu83”)).
The teachings of Yoo/Kim have been discussed above.
Re claims 15 & 16, Yoo/Kim does not explicitly teach wherein: each first bonding pad of the plurality of first bonding pads is directly bonded to each second bonding pad of the plurality of second bonding pads; and the first silicon insulating layer is directly bonded to the second silicon insulating layer.
Yu83 teaches, Fig. 2C, [0037], each first bonding pad of the plurality of first bonding pads (60) is directly bonded to each second bonding pad of the plurality of second bonding pads (22B); and the first silicon insulating layer (58) is directly bonded to the second silicon insulating layer (24B).
As taught by Yu83, one of ordinary skill in the art would utilize & modify the above teaching teach to obtain directly bonding between pads and silicon insulating layers as claimed, because it aids in improving integration density, stability and reliability in the formed structure.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu83 in combination Yoo/Kim due to above reason.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 2015/0214191, Figs. 13-14) discloses package with stacked dies bonded onto a wafer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/28/26
Prosecution Insights